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1 of 87 041400 multi-chip module features ? twelve (12) completely independent e1 framers in one small 27 mm x 27 mm package ? each multi-chip module (mcm) contains three ds21q44 quad e1 framer die ? each quad framer can be concatenated into a single 8.192 mhz backplane data stream ? 300?pin mcm 1.27 mm pitch bga package (27 mm x 27 mm) ? low power 3.3v cmos with 5v tolerant input & outputs framer features ? all framers are fully independent; transmit and receive sections of each framer are fully independent ? frames to fas, cas, ccs, and crc4 formats ? each framer contains dual two?frame elastic store slip buffers that can connect to asynchronous backplanes up to 8.192 mhz ? 8?bit parallel control port that can be used directly on either multiplexed or non? multiplexed buses (intel or motorola) ? easy access to si and sa bits ? extracts and inserts cas signaling functional diagram receive framer elastic store transmit formatter elastic store framer #1 framer #2 framer #3 control port framer #12 ?? ?? ?? ?? ? large counters for bipolar and code violations, crc4 code word errors, fas word errors, and e-bits ? programmable output clocks for fractional e1, per channel loopback, h0 and h12 applications ? integral hdlc controller with 64-byte buffers. configurable for sa bits or ds0 operation ? detects and generates ais, remote alarm, and remote multiframe alarms ? ieee 1149.1 support description the DS21FT40 mcm offers a high density packaging arrangement for the ds21q44 e1 enhanced quad framer. three ds21q44 silicon die are packaged in a multi-chip module (mcm) with the electrical connections as shown in figure 1-1. the DS21FT40 is closely related to the ds21ft44. most of the functions of the ds21ft44 are available on the DS21FT40. the differences are listed in table 1-1. table 2-1 lists all of the signals on the mcm. the ds21q44 e1 framer is an enhanced version of the ds21q43 quad e1 framer. each ds21q44 die contains four framers that are configured and read through a common microprocessor-compatible parallel port. each framer consists of a receive framer, receive elastic store, transmit formatter and transmit elastic store. all four framers in the ds21q44 are totally independent, they do not share a common framing synchronizer. also, the transmit and receive sides of each framer are totally independent. the DS21FT40 four x three 12 channel e1 frame r www.dalsemi.com
DS21FT40 2 of 87 dual two-frame elastic stores contained in each of the four framers can be independently enabled and disabled as required. the device fully meets all of the latest e1 specifications including ccitt/itu g.704, g.706, g.962, and i.431 as well as ets 300 011 and ets 300 233. functional description the receive side in each framer locates fas frame and crc and cas multiframe boundaries as well as detects incoming alarms including, carrier loss, loss of synchronization, ais and remote alarm. if needed, the receive side elastic store can be enabled in order to absorb the phase and frequency differences between the recovered e1 data stream and an asynchronous backplane clock which is provided at the rsysclk input. the clock applied at the rsysclk input can be either a 2.048 mhz clock or a 1.544 mhz clock. the rsysclk can be a burst clock with speeds up to 8.192 mhz. the transmit side in each framer is totally independent from the receive side in both the clock requirements and characteristics. data off of a backplane can be passed through a transmit side elastic store if necessary. the transmit formatter will provide the necessary frame/multiframe data overhead for e1 transmission. reader?s note: this data sheet assumes a particular nomenclature of the e1 operating environment. in each 125 us frame, there are 32 8?bit timeslots numbered 0 to 31. timeslot 0 is transmitted first and received first. these 32 timeslots are also referred to as channels with a numbering scheme of 1 to 32. timeslot 0 is identical to channel 1, timeslot 1 is identical to channel 2, and so on. each timeslot (or channel) is made up of 8 bits which are numbered 1 to 8. bit number 1 is the msb and is transmitted first. bit number 8 is the lsb and is transmitted last. throughout this data sheet, the following abbreviations will be used: fas frame alignment signal cas channel associated signaling mf multiframe si international bits crc4 cyclical redundancy check ccs common channel signaling sa additional bits e-bit crc4 error bits
DS21FT40 3 of 87 DS21FT40 schematic figure 1-1 rclk1/2/3/4 rpos1/2/3/4 rneg1/2/3/4 rser1/2/3/4 rsync1/2/3/4 rsysclk1/2/3/4 tclk1/2/3/4 tneg1/2/3/4 tpos1/2/3/4 tser1/2/3/4 tssync1/2/3/4 tsync1/2/3/4 tsysclk1/2/3/4 tlink0/1/2/3 int* fms d0 to d7 a0 to a7 rd* wr* bts mux cs* fs0/fs1 test signals not connected & left open circuited include: rlos/lotc rlink rlclk rchblk rchclk rfsync tlclk tchclk tchblk rsig tsig 8mclk clksi jtrst* jtms jtclk jtdi jtdo ds21q44 # 1 rclk5/6/7/8 rpos5/6/7/8 rneg5/6/7/8 rser5/6/7/8 rsync5/6/7/8 rsysclk5/6/7/8 tclk5/6/7/8 tneg5/6/7/8 tpos5/6/7/8 tser5/6/7/8 tssync5/6/7/8 tsync5/6/7/8 tsysclk5/6/7/8 int* d0 to d7 a0 to a7 rd* wr* bts mux cs* fs0/fs1 test signals not connected & left open circuited include: rlos/lotc rlink rlclk rchblk rchclk rfsync tlclk tchclk tchblk rsig tsig 8mclk clksi jtrst* jtms jtclk jtdi jtdo ds21q44 # 2 2 8 8 see connecting page dvdd dvss dvss tlink0/1/2/3 fms dvss dvss dvdd rmsync5/6/7/8 rmsync1/2/3/4
DS21FT40 4 of 87 DS21FT40 schematic figure 1-1 (continued) changes in DS21FT40 compared to ds21ft44 table 1-1 1. the sysclk pins have been separated into tsysclk and rsysclk pins. 2. rmsync pins have been added. 3. fms tied to vdd. 4. the following signals are not available: rsig / tsig / 8mclk / clksi / jtrst* / jtms / jtclk / jtdi / jtdo rclk9/10/11/12 rpos9/10/11/12 rneg9/10/11/12 rser9/10/11/12 rsync9/10/11/12 rsysclk9/10/11/12 tclk9/10/11/12 tneg9/10/11/12 tpos9/10/11/12 tser9/10/11/12 tssync9/10/11/12 tsync9/10/11/12 tsysclk9/10/11/12 tlink0/1/2/3 int* fms d0 to d7 a0 to a7 rd* wr* bts mux cs* fs0/fs1 test signals not connected & left open circuited include: rlos/lotc rlink rlclk rchblk rchclk rfsync tlclk tchclk tchblk rsig tsig 8mclk clksi jtrst* jtms jtclk jtdi jtdo ds21q44 # 3 dvdd dvss dvss see connecting page rmsync9/10/11/12
DS21FT40 5 of 87 DS21FT40 enhanced 12-channel e1 framer figure 1-2 vss vdd framer #2 framer #3 framer #1 parallel & test control port (routed to all blocks) d0 to d7 / ad0 to ad7 fs1 bts int* wr* (r/w*) rd* (ds*) fs0 cs* test ale (as)/ a6 a0 to a5, a7 mux 7 8 f r a m e r l o o p b a c k a i s g e n e r a t i o n h d b 3 e n c o d e c r c 4 g e n e r a t i o n f a s w o r d i n s e r t i o n receive side framer transmit side formatter b p v c o u n t e r a l a r m d e t e c t i o n p e r - c h a n n e l c o d e i n s e r t elastic store e - b i t c o u n t e r sync data clock sync data clock tsync tclk tser rmsync tssync tsysclk rser rsysclk rsync sa extraction timing control elastic store sync control timing control h d b 3 d e c o d e r s y n c h r o n i z e r c r c e r r o r c o u n t e r f a s e r r o r c o u n t e r s i g n a l i n g e x t r a c t i o n s a a n d s i e x t r a c t i o n signaling buffer hardware signaling insertion r e m o t e l o o p b a c k p e r - c h a n n e l c o d e i n s e r t p e r - c h a n n e l l o o p b a c k 64-byte buffer rpos rclk rneg tpos tneg hdlc engine ds0 insertion power lotc det & mux sa insertion 64-byte buffer hdlc engine ds0 insertion s i b i t i n s e r t i o n e - b i t i n s e r t i o n s a i n s e r t i o n s i g n a l i n g i n s e r t i o n framer #12
DS21FT40 6 of 87 table of contents description.................................................................................................................... ...................................................... 1 1. DS21FT40 pin description..................................................................................................... .................................. 8 2. ds21ft44 pin function description............................................................................................ ................... 16 3. DS21FT40 register map........................................................................................................ .................................. 19 4. parallel port................................................................................................................ .......................................... 24 5. control, id and test registers............................................................................................... ...................... 24 6. status and information registers ............................................................................................. ............... 33 7. error count registers ........................................................................................................ .............................. 39 8. ds0 monitoring function...................................................................................................... ............................ 41 9. signaling operation.......................................................................................................... .................................. 44 9.1 processor based signaling ................................................................................................... ..................... 44 9.2 hardware based signaling .................................................................................................... .................... 47 10. per?channel code generation and loopback................................................................................ 47 10.1 transmit side code generation.............................................................................................. ................. 47 10.1.1 simple idle code insertion and per?channel loopback...................................................................... ............. 47 10.1.2 per?channel code insertion ............................................................................................... .............................. 48 10.2 receive side code generation ............................................................................................... ................... 49 11. clock blocking registers .................................................................................................... ...................... 50 12. elastic stores operation .................................................................................................... ........................ 50 12.1 receive side............................................................................................................... .......................................... 51 12.2 transmit side .............................................................................................................. ....................................... 51 13. additional (sa) and international (si) bit operation ................................................................ 51 13.1 internal register scheme based on double?frame ..................................................................... 51 13.2 internal register scheme based on crc4 multiframe................................................................ 53 14. hdlc controller for the sa bits or ds0...................................................................................... ....... 55 14.1 g eneral o verview ............................................................................................................................... ................... 55 14.2 hdlc s tatus r egisters ............................................................................................................................... .......... 56 14.3 b asic o peration d etails ............................................................................................................................... ......... 57 14.4 hdlc r egister d escription ............................................................................................................................... ... 58 15. interleaved pcm bus operation ............................................................................................... ............... 64 16. timing diagrams............................................................................................................. .................................... 67 17. operating parameters........................................................................................................ ........................... 75 18. DS21FT40 mechanical dimensions.............................................................................................. ................ 86
DS21FT40 7 of 87 document revision history revision notes 5-18-99 initial release 8-19-99 concatenated DS21FT40 and ds21q44 data sheets 8-26-99 remove rchblk pins. 2-17-00 corrected error in figure 1-1 (removed rchblk pins).
DS21FT40 8 of 87 1. DS21FT40 pin description pin description sorted by pin number table 2-1 lead symbols i/o description g20 a0 i address bus bit 0 (lsb). h20 a1 i address bus bit 1. g19 a2 i address bus bit 2. h19 a3 i address bus bit 3. g18 a4 i address bus bit 4. h18 a5 i address bus bit 5. g17 a6 i address bus bit 6. h17 a7 i address bus bit 7 (msb). w15 bts i bus timing select. 0 = intel / 1 = motorola. t8 cs1* i chip select for quad framer 1. y4 cs2* i chip select for quad framer 2. y15 cs3* i chip select for quad framer 3. l20 d0 i/o data bus bit 0 (lsb). m20 d1 i/o data bus bit 1. l19 d2 i/o data bus bit 2. m19 d3 i/o data bus bit 3. l18 d4 i/o data bus bit 4. m18 d5 i/o data bus bit 5. l17 d6 i/o data bus bit 6. m17 d7 i/o data bus bit 7 (msb). c7 dvdd1 ? digital positive supply for framer 1. e4 dvdd1 ? digital positive supply for framer 1. d2 dvdd1 ? digital positive supply for framer 1. k3 dvdd2 ? digital positive supply for framer 2. u7 dvdd2 ? digital positive supply for framer 2. p2 dvdd2 ? digital positive supply for framer 2. v19 dvdd3 ? digital positive supply for framer 3. t12 dvdd3 ? digital positive supply for framer 3. l16 dvdd3 ? digital positive supply for framer 3. e9 dvss1 ? digital signal ground for framer 1. a6 dvss1 ? digital signal ground for framer 1. d5 dvss1 ? digital signal ground for framer 1. u3 dvss2 ? digital signal ground for framer 2. k4 dvss2 ? digital signal ground for framer 2. u8 dvss2 ? digital signal ground for framer 2. u4 dvss3 ? digital signal ground for framer 3. r16 dvss3 ? digital signal ground for framer 3. y20 dvss3 ? digital signal ground for framer 3. y14 fs0 i framer select 0 for the parallel control port. w14 fs1 i framer select 1 for the parallel control port. g16 int* o interrupt for all four quad framers. p17 mux i bus operation select. 0 = non-multiplexed bus / 1 =
DS21FT40 9 of 87 lead symbols i/o description multiplexed bus a2 rclk1 i receive clock for framer 1 k1 rclk2 i receive clock for framer 2. d10 rclk3 i receive clock for framer 3. b9 rclk4 i receive clock for framer 4. m3 rclk5 i receive clock for framer 5. v1 rclk6 i receive clock for framer 6. w6 rclk7 i receive clock for framer 7. j3 rclk8 i receive clock for framer 8. t9 rclk9 i receive clock for framer 9. w10 rclk10 i receive clock for framer 10. y18 rclk11 i receive clock for framer 11. n17 rclk12 i receive clock for framer 12. e18 rd* i read input. d3 rmsync1 o receive multiframe sync from framer 1 g2 rmsync2 o receive multiframe sync from framer 2 d4 rmsync3 o receive multiframe sync from framer 3 d8 rmsync4 o receive multiframe sync from framer 4 n2 rmsync5 o receive multiframe sync from framer 5 v4 rmsync6 o receive multiframe sync from framer 6 v6 rmsync7 o receive multiframe sync from framer 7 k5 rmsync8 o receive multiframe sync from framer 8 u10 rmsync9 o receive multiframe sync from framer 9 y11 rmsync10 o receive multiframe sync from framer 10 w19 rmsync11 o receive multiframe sync from framer 11 u20 rmsync12 o receive multiframe sync from framer 12 b2 rneg1 i receive negative data for framer 1. h2 rneg2 i receive negative data for framer 2. d9 rneg3 i receive negative data for framer 3. a9 rneg4 i receive negative data for framer 4. m2 rneg5 i receive negative data for framer 5. v3 rneg6 i receive negative data for framer 6. v7 rneg7 i receive negative data for framer 7. p3 rneg8 i receive negative data for framer 8. u9 rneg9 i receive negative data for framer 9. w11 rneg10 i receive negative data for framer 10. w17 rneg11 i receive negative data for framer 11. t20 rneg12 i receive negative data for framer 12. a1 rpos1 i receive positive data for framer 1. h1 rpos2 i receive positive data for framer 2. h4 rpos3 i receive positive data for framer 3. c9 rpos4 i receive positive data for framer 4. m1 rpos5 i receive positive data for framer 5. w2 rpos6 i receive positive data for framer 6. v5 rpos7 i receive positive data for framer 7.
DS21FT40 10 of 87 lead symbols i/o description p4 rpos8 i receive positive data for framer 8. t10 rpos9 i receive positive data for framer 9. v11 rpos10 i receive positive data for framer 10. y19 rpos11 i receive positive data for framer 11. r19 rpos12 i receive positive data for framer 12. c1 rser1 o receive serial data from framer 1. h3 rser2 o receive serial data from framer 2. c6 rser3 o receive serial data from framer 3. c8 rser4 o receive serial data from framer 4. p1 rser5 o receive serial data from framer 5. w4 rser6 o receive serial data from framer 6. t7 rser7 o receive serial data from framer 7. n4 rser8 o receive serial data from framer 8. u11 rser9 o receive serial data from framer 9. y12 rser10 o receive serial data from framer 10. v16 rser11 o receive serial data from framer 11. t16 rser12 o receive serial data from framer 12. b1 rsync1 i/o receive frame/multiframe sync for framer 1. g1 rsync2 i/o receive frame/multiframe sync for framer 2. d6 rsync3 i/o receive frame/multiframe sync for framer 3. a7 rsync4 i/o receive frame/multiframe sync for framer 4. n3 rsync5 i/o receive frame/multiframe sync for framer 5. y2 rsync6 i/o receive frame/multiframe sync for framer 6. u5 rsync7 i/o receive frame/multiframe sync for framer 7. j4 rsync8 i/o receive frame/multiframe sync for framer 8. t11 rsync9 i/o receive frame/multiframe sync for framer 9. v13 rsync10 i/o receive frame/multiframe sync for framer 10. v15 rsync11 i/o receive frame/multiframe sync for framer 11. p18 rsync12 i/o receive frame/multiframe sync for framer 12. b5 rsysclk1 i receive system clock for framer 1. e2 rsysclk2 i receive system clock for framer 2. e5 rsysclk3 i receive system clock for framer 3. b8 rsysclk4 i receive system clock for framer 4. m4 rsysclk5 i receive system clock for framer 5. t2 rsysclk6 i receive system clock for framer 6. y5 rsysclk7 i receive system clock for framer 7. w3 rsysclk8 i receive system clock for framer 8. t4 rsysclk9 i receive system clock for framer 9. y9 rsysclk10 i receive system clock for framer 10. u12 rsysclk11 i receive system clock for framer 11. r17 rsysclk12 i receive system clock for framer 12. d1 tclk1 i transmit clock for framer 1. h5 tclk2 i transmit clock for framer 2. c5 tclk3 i transmit clock for framer 3. a5 tclk4 i transmit clock for framer 4.
DS21FT40 11 of 87 lead symbols i/o description r1 tclk5 i transmit clock for framer 5. y3 tclk6 i transmit clock for framer 6. t6 tclk7 i transmit clock for framer 7. k2 tclk8 i transmit clock for framer 8. u13 tclk9 i transmit clock for framer 9. y13 tclk10 i transmit clock for framer 10. t18 tclk11 i transmit clock for framer 11. p16 tclk12 i transmit clock for framer 12. a13 test i tri-state. 0 = do not tri-state / 1 = tri-state all outputs & i/o signals c3 tneg1 o transmit negative data from framer 1. j1 tneg2 o transmit negative data from framer 2. f5 tneg3 o transmit negative data from framer 3. a10 tneg4 o transmit negative data from framer 4. l1 tneg5 o transmit negative data from framer 5. v2 tneg6 o transmit negative data from framer 6. v8 tneg7 o transmit negative data from framer 7. p5 tneg8 o transmit negative data from framer 8. u14 tneg9 o transmit negative data from framer 9. v12 tneg10 o transmit negative data from framer 10. w18 tneg11 o transmit negative data from framer 11. t19 tneg12 o transmit negative data from framer 12. b3 tpos1 o transmit positive data from framer 1. j2 tpos2 o transmit positive data from framer 2. j5 tpos3 o transmit positive data from framer 3. b10 tpos4 o transmit positive data from framer 4. l2 tpos5 o transmit positive data from framer 5. w1 tpos6 o transmit positive data from framer 6. w7 tpos7 o transmit positive data from framer 7. r3 tpos8 o transmit positive data from framer 8. t14 tpos9 o transmit positive data from framer 9. y10 tpos10 o transmit positive data from framer 10. v18 tpos11 o transmit positive data from framer 11. v20 tpos12 o transmit positive data from framer 12. b4 tser1 i transmit serial data for framer 1. e1 tser2 i transmit serial data for framer 2. f3 tser3 i transmit serial data for framer 3. d7 tser4 i transmit serial data for framer 4. l5 tser5 i transmit serial data for framer 5. t1 tser6 i transmit serial data for framer 6. y6 tser7 i transmit serial data for framer 7. t3 tser8 i transmit serial data for framer 8. m16 tser9 i transmit serial data for framer 9. w9 tser10 i transmit serial data for framer 10. w16 tser11 i transmit serial data for framer 11.
DS21FT40 12 of 87 lead symbols i/o description w20 tser12 i transmit serial data for framer 12. a3 tssync1 i transmit system sync for framer 1. f2 tssync2 i transmit system sync for framer 2. g5 tssync3 i transmit system sync for framer 3. e8 tssync4 i transmit system sync for framer 4. l4 tssync5 i transmit system sync for framer 5. u1 tssync6 i transmit system sync for framer 6. y7 tssync7 i transmit system sync for framer 7. r4 tssync8 i transmit system sync for framer 8. t15 tssync9 i transmit system sync for framer 9. w8 tssync10 i transmit system sync for framer 10. y17 tssync11 i transmit system sync for framer 11. u19 tssync12 i transmit system sync for framer 12. e3 tsync1 i/o transmit sync for framer 1. f4 tsync2 i/o transmit sync for framer 2. e7 tsync3 i/o transmit sync for framer 3. a4 tsync4 i/o transmit sync for framer 4. r2 tsync5 i/o transmit sync for framer 5. w5 tsync6 i/o transmit sync for framer 6. t5 tsync7 i/o transmit sync for framer 7. m5 tsync8 i/o transmit sync for framer 8. t13 tsync9 i/o transmit sync for framer 9. w13 tsync10 i/o transmit sync for framer 10. u16 tsync11 i/o transmit sync for framer 11. n16 tsync12 i/o transmit sync for framer 12. c4 tsysclk1 i transmit system clock for framer 1. f1 tsysclk2 i transmit system clock for framer 2. g4 tsysclk3 i transmit system clock for framer 3. c10 tsysclk4 i transmit system clock for framer 4. l3 tsysclk5 i transmit system clock for framer 5. u2 tsysclk6 i transmit system clock for framer 6. v9 tsysclk7 i transmit system clock for framer 7. r5 tsysclk8 i transmit system clock for framer 8. u15 tsysclk9 i transmit system clock for framer 9. v10 tsysclk10 i transmit system clock for framer 10. u18 tsysclk11 i transmit system clock for framer 11. r18 tsysclk12 i transmit system clock for framer 12. y16 wr* i write input. a11 nc ? no connect a12 nc ? no connect a14 nc ? no connect a15 nc ? no connect a16 nc ? no connect a17 nc ? no connect a18 nc ? no connect
DS21FT40 13 of 87 lead symbols i/o description a19 nc ? no connect a20 nc ? no connect a8 nc ? no connect b11 nc ? no connect b12 nc ? no connect b13 nc ? no connect b14 nc ? no connect b15 nc ? no connect b16 nc ? no connect b17 nc ? no connect b18 nc ? no connect b19 nc ? no connect b20 nc ? no connect b6 nc ? no connect b7 nc ? no connect c11 nc ? no connect c12 nc ? no connect c13 nc ? no connect c14 nc ? no connect c15 nc ? no connect c16 nc ? no connect c17 nc ? no connect c18 nc ? no connect c19 nc ? no connect c2 nc ? no connect c20 nc ? no connect d11 nc ? no connect d12 nc ? no connect d13 nc ? no connect d14 nc ? no connect d15 nc ? no connect d16 nc ? no connect d17 nc ? no connect d18 nc ? no connect d19 nc ? no connect d20 nc ? no connect e10 nc ? no connect e11 nc ? no connect e12 nc ? no connect e13 nc ? no connect e14 nc ? no connect e15 nc ? no connect e16 nc ? no connect e17 nc ? no connect e19 nc ? no connect
DS21FT40 14 of 87 lead symbols i/o description e20 nc ? no connect e6 nc ? no connect f16 nc ? no connect f17 nc ? no connect f18 nc ? no connect f19 nc ? no connect f20 nc ? no connect g3 nc ? no connect h16 nc ? no connect j16 nc ? no connect j17 nc ? no connect j18 nc ? no connect j19 nc ? no connect j20 nc ? no connect k16 nc ? no connect k17 nc ? no connect k18 nc ? no connect k19 nc ? no connect k20 nc ? no connect n1 nc ? no connect n18 nc ? no connect n19 nc ? no connect n20 nc ? no connect n5 nc ? no connect p19 nc ? no connect p20 nc ? no connect r20 nc ? no connect t17 nc ? no connect u17 nc ? no connect u6 nc ? no connect v14 nc ? no connect v17 nc ? no connect w12 nc ? no connect y1 nc ? no connect y8 nc ? no connect
DS21FT40 15 of 87 DS21FT40 pcb land pattern figure 2-1 the diagram shown below is the lead pattern that will be placed on the target pcb. this is the same pattern that would be seen as viewed through the mcm from the top. 1234567891011121314151617181920 a rpos 1 rclk 1 ts sync1 tsync 4 tclk 4 dvss 1 rsync 4 nc rneg 4 tneg 4 nc nc test ns ns nc nc nc nc nc b rsync 1 rneg 1 tpos 1 tser 1 rsys clk 1 nc nc rsys clk 4 rclk 4 tpos 4 nc nc nc nc nc nc nc nc nc nc c rser 1 nc tneg 1 tsys clk 1 tclk 3 rser 3 dvdd 1 rser4 rpos 4 tsys clk 4 nc nc nc nc ns nc nc nc nc nc d tclk 1 dvdd 1 rm sync 1 rm sync 3 dvss 1 rsync 3 tser 4 rm sync4 rneg 3 rclk 3 nc nc nc nc nc nc nc nc nc nc e tser 2 rsys clk 2 tsync 1 dvdd 1 rsys clk 3 nc tsync 3 ts sync 4 dvss 1 nc nc nc nc nc nc nc nc rd* nc nc f tsys clk 2 ts sync 2 tser 3 tsync 2 tneg 3 nc nc nc nc nc g rsync 2 rm sync 2 nc tsys clk 3 ts sync 3 int* a6 a4 a2 a0 h rpos 2 rneg 2 rser 2 rpos 3 tclk 2 nc a7 a5 a3 a1 j tneg 2 tpos 2 rclk 8 rsync 8 tpos 3 nc nc nc nc nc k rclk 2 tclk 8 dvdd 2 dvss 2 rm sync 8 nc nc nc nc nc l tneg 5 tpos 5 tsys clk 5 ts sync 5 tser 5 dvdd 3 d6 d4 d2 d0 m rpos 5 rneg 5 rclk 5 rsys clk 5 tsync 8 tser 9 d7 d5 d3 d1 n nc rm sync 5 rsync 5 rser 8 nc tsync 12 rclk 12 nc nc nc p rser 5 dvdd 2 rneg 8 rpos 8 tneg 8 tclk 12 mux rsync 12 nc nc r tclk 5 tsync 5 tpos 8 ts sync 8 tsys clk 8 dvss 3 rsys clk 12 tsys clk 12 rpos 12 nc t tser 6 rsys clk 6 tser 8 rsys clk 9 tsync 7 tclk 7 rser 7 cs1* rclk 9 rpos 9 rsync 9 dvdd 3 tsync 9 tpos 9 ts sync 9 rser 12 nc tclk 11 tneg 12 rneg 12 u ts sync 6 tsys clk 6 dvss 2 dvss 3 rsync 7 nc dvdd 2 dvss 2 rneg 9 rm sync 9 rser 9 rsys clk 11 tclk 9 tneg 9 tsys clk 9 tsync 11 nc tsys clk 11 ts sync 12 rm sync 12 v rclk 6 tneg 6 rneg 6 rm sync 6 rpos 7 rm sync 7 rneg 7 tneg 7 tsys clk 7 tsys clk 10 rpos 10 tneg 10 rsync 10 nc rsync 11 rser 11 nc tpos 11 dvdd 3 tpos 12 w tpos 6 rpos 6 rsys clk 8 rser 6 tsync 6 rclk 7 tpos 7 ts sync 10 tser 10 rclk 10 rneg 10 nc tsync 10 fs1 bts tser 11 rneg 11 tneg 11 rm sync 11 tser 12 y nc rsync 6 tclk 6 cs2* rsys clk 7 tser 7 ts sync 7 nc rsys clk 10 tpos 10 rm sync 10 rser 10 tclk 10 fs0 cs3* wr* ts sync 11 rclk 11 rpos 11 dvss 3
DS21FT40 16 of 87 2. ds21ft44 pin function description transmit side pins signal name: tclk signal description: transmit clock signal type: input a 2.048 mhz primary clock. used to clock data through the transmit side formatter. signal name: tser signal description: transmit serial data signal type: input transmit nrz serial data. sampled on the falling edge of tclk when the transmit side elastic store is disabled. sampled on the falling edge of tsysclk when the transmit side elastic store is enabled. signal name: tsysclk signal description: transmit system clock signal type: input 1.544 mhz or 2.048 mhz clock. only used when the transmit side elastic store function is enabled. should be tied low in applications that do not use the transmit side elastic store. can be burst at rates up to 8.192 mhz. signal name: tsync signal description: transmit sync signal type: input /output a pulse at this pin will establish either frame or multiframe boundaries for the transmit side. this pin can also be programmed to output either a frame or multiframe pulse. always synchronous with tclk. signal name: tssync signal description: transmit system sync signal type: input only used when the transmit side elastic store is enabled. a pulse at this pin will establish either frame or multiframe boundaries for the transmit side. should be tied low in applications that do not use the transmit side elastic store. always synchronous with tsysclk. signal name: tpos signal description: transmit positive data output signal type: output updated on the rising edge of tclk with the bipolar data out of the transmit side formatter. can be programmed to source nrz data via the output data format (tcr1.7) control bit. signal name: tneg signal description: transmit negative data output signal type: output updated on the rising edge of tclk with the bipolar data out of the transmit side formatter.
DS21FT40 17 of 87 receive side pins signal name: rclk signal description: receive clock input signal type: input 2.048 mhz clock that is used to clock data through the receive side framer. signal name: rser signal description: receive serial data signal type: output received nrz serial data. updated on rising edges of rclk when the receive side elastic store is disabled. updated on the rising edges of rsysclk when the receive side elastic store is enabled. signal name: rsync signal description: receive sync signal type: input /output an extracted pulse, one rclk wide, is output at this pin which identifies either frame or cas/crc multiframe boundaries. if the receive side elastic store is enabled, then this pin can be enabled to be an input at which a frame or multiframe boundary pulse synchronous with rsysclk is applied. signal name: rmsync signal description: receive multiframe sync signal type: output an extracted pulse, one rsysclk wide, is output at this pin which identifies multiframe boundaries. if the receive side elastic store is disabled, then this output will output multiframe boundaries associated with rclk. signal name: rsysclk signal description: receive system clock signal type: input 1.544 mhz or 2.048 mhz clock. only used when the elastic store function is enabled. should be tied low in applications that do not use the elastic store. can be burst at rates up to 8.192 mhz. signal name: rpos signal description: receive positive data input signal type: input sampled on the falling edge of rclk for data to be clocked through the receive side framer. rpos and rneg can be tied together for an nrz interface. connecting rpos to rneg disables the bipolar violation monitoring circuitry. signal name: rneg signal description: receive negative data input signal type: input sampled on the falling edge of rclk for data to be clocked through the receive side framer. rpos and rneg can be tied together for an nrz interface. connecting rpos to rneg disables the bipolar violation monitoring circuitry.
DS21FT40 18 of 87 parallel control port pins signal name: int* signal description: interrupt signal type: output flags host controller during conditions and change of conditions defined in the status registers 1 and 2 and the fdl status register. active low, open drain output. signal name: mux signal description: bus operation signal type: input set low to select non?multiplexed bus operation. set high to select multiplexed bus operation. signal name: d0 to d7 / ad0 to ad7 signal description: data bus or address/data bus signal type: input /output in non?multiplexed bus operation (mux = 0), serves as the data bus. in multiplexed bus operation (mux = 1), serves as a 8?bit multiplexed address / data bus. signal name: a0 to a5, a7 signal description: address bus signal type: input in non?multiplexed bus operation (mux = 0), serves as the address bus. in multiplexed bus operation (mux = 1), these pins are not used and should be tied low. signal name: ale (as) / a6 signal description: address latch enable (address strobe) or a6 signal type: input in non?multiplexed bus operation (mux = 0), serves as address bit 6. in multiplexed bus operation (mux = 1), serves to demultiplex the bus on a positive?going edge. signal name: bts signal description: bus type select signal type: input strap high to select motorola bus timing; strap low to select intel bus timing. this pin controls the function of the rd*(ds*), ale(as), and wr*(r/w*) pins. if bts = 1, then these pins assume the function listed in parenthesis (). signal name: rd* (ds) signal description: read input (data strobe) signal type: input rd* is an active low signal and ds is an active high signal. signal name: fs0 and fs1 signal description: framer selects signal type: input selects which of the four framers is to be accessed for a specific ds21q44 die.
DS21FT40 19 of 87 signal name: cs1* to cs3* signal description: chip select signal type: input must be low to read or write to a specific ds21q44 die. these are active low signals. signal name: wr* (r/w*) signal description: write input (read/write) signal type: input wr* is an active low signal. test access port pins signal name: test signal description: 3?state control signal type: input set high to 3?state all output and i/o pins (including the parallel control port). set low for normal operation. useful in board level testing. supply pins signal name: vdd signal description: positive supply signal type: supply 2.97 to 3.63 volts. signal name: vss signal description: signal ground signal type: supply 0.0 volts. 3. DS21FT40 register map register map for each quad framer sorted by address table 3-1 address r/w register name register abbreviation 00 r bpv or code violation count 1 vcr1 01 r bpv or code violation count 2 vcr2 02 r crc4 error count 1 / fas error count 1 crccr1 03 r crc4 error count 2 crccr2 04 r e-bit count 1 / fas error count 2 ebcr1 05 r e-bit count 2 ebcr2 06 r/w status 1 sr1 07 r/w status 2 sr2 08 r/w receive information rir 09 r/w test 2 test2 (set to 00h) 0a ? not used (set to 00h) 0b ? not used (set to 00h) 0c ? not used (set to 00h)
DS21FT40 20 of 87 address r/w register name register abbreviation 0d ? not used (set to 00h) 0e ? not used (set to 00h) 0f r device id idr 10 r/w receive control 1 rcr1 11 r/w receive control 2 rcr2 12 r/w transmit control 1 tcr1 13 r/w transmit control 2 tcr2 14 r/w common control 1 ccr1 15 r/w test 1 test1 (set to 00h) 16 r/w interrupt mask 1 imr1 17 r/w interrupt mask 2 imr2 18 ? not used (set to 00h) 19 ? not used (set to 00h) 1a r/w common control 2 ccr2 1b r/w common control 3 ccr3 1c r/w transmit sa bit control tsacr 1d r/w common control 6 ccr6 1e r synchronizer status ssr 1f r receive non-align frame rnaf 20 r/w transmit align frame taf 21 r/w transmit non-align frame tnaf 22 r/w transmit channel blocking 1 (not applicable to DS21FT40 ? write to 00h.) tcbr1 23 r/w transmit channel blocking 2 (not applicable to DS21FT40 ? write to 00h.) tcbr2 24 r/w transmit channel blocking 3 (not applicable to DS21FT40 ? write to 00h.) tcbr3 25 r/w transmit channel blocking 4 (not applicable to DS21FT40 ? write to 00h.) tcbr4 26 r/w transmit idle 1 tir1 27 r/w transmit idle 2 tir2 28 r/w transmit idle 3 tir3 29 r/w transmit idle 4 tir4 2a r/w transmit idle definition tidr 2b r/w receive channel blocking 1 rcbr1 2c r/w receive channel blocking 2 rcbr2 2d r/w receive channel blocking 3 rcbr3 2e r/w receive channel blocking 4 rcbr4 2f r receive align frame raf 30 r receive signaling 1 rs1
DS21FT40 21 of 87 address r/w register name register abbreviation 31 r receive signaling 2 rs2 32 r receive signaling 3 rs3 33 r receive signaling 4 rs4 34 r receive signaling 5 rs5 35 r receive signaling 6 rs6 36 r receive signaling 7 rs7 37 r receive signaling 8 rs8 38 r receive signaling 9 rs9 39 r receive signaling 10 rs10 3a r receive signaling 11 rs11 3b r receive signaling 12 rs12 3c r receive signaling 13 rs13 3d r receive signaling 14 rs14 3e r receive signaling 15 rs15 3f r receive signaling 16 rs16 40 r/w transmit signaling 1 ts1 41 r/w transmit signaling 2 ts2 42 r/w transmit signaling 3 ts3 43 r/w transmit signaling 4 ts4 44 r/w transmit signaling 5 ts5 45 r/w transmit signaling 6 ts6 46 r/w transmit signaling 7 ts7 47 r/w transmit signaling 8 ts8 48 r/w transmit signaling 9 ts9 49 r/w transmit signaling 10 ts10 4a r/w transmit signaling 11 ts11 4b r/w transmit signaling 12 ts12 4c r/w transmit signaling 13 ts13 4d r/w transmit signaling 14 ts14 4e r/w transmit signaling 15 ts15 4f r/w transmit signaling 16 ts16 50 r/w transmit si bits align frame tsiaf 51 r/w transmit si bits non-align frame tsinaf 52 r/w transmit remote alarm bits tra 53 r/w transmit sa4 bits tsa4 54 r/w transmit sa5 bits tsa5 55 r/w transmit sa6 bits tsa6 56 r/w transmit sa7 bits tsa7 57 r/w transmit sa8 bits tsa8 58 r receive si bits align frame rsiaf 59 r receive si bits non-align frame rsinaf 5a r receive remote alarm bits rra 5b r receive sa4 bits rsa4 5c r receive sa5 bits rsa5
DS21FT40 22 of 87 address r/w register name register abbreviation 5d r receive sa6 bits rsa6 5e r receive sa7 bits rsa7 5f r receive sa8 bits rsa8 60 r/w transmit channel 1 tc1 61 r/w transmit channel 2 tc2 62 r/w transmit channel 3 tc3 63 r/w transmit channel 4 tc4 64 r/w transmit channel 5 tc5 65 r/w transmit channel 6 tc6 66 r/w transmit channel 7 tc7 67 r/w transmit channel 8 tc8 68 r/w transmit channel 9 tc9 69 r/w transmit channel 10 tc10 6a r/w transmit channel 11 tc11 6b r/w transmit channel 12 tc12 6c r/w transmit channel 13 tc13 6d r/w transmit channel 14 tc14 6e r/w transmit channel 15 tc15 6f r/w transmit channel 16 tc16 70 r/w transmit channel 17 tc17 71 r/w transmit channel 18 tc18 72 r/w transmit channel 19 tc19 73 r/w transmit channel 20 tc20 74 r/w transmit channel 21 tc21 75 r/w transmit channel 22 tc22 76 r/w transmit channel 23 tc23 77 r/w transmit channel 24 tc24 78 r/w transmit channel 25 tc25 79 r/w transmit channel 26 tc26 7a r/w transmit channel 27 tc27 7b r/w transmit channel 28 tc28 7c r/w transmit channel 29 tc29 7d r/w transmit channel 30 tc30 7e r/w transmit channel 31 tc31 7f r/w transmit channel 32 tc32 80 r/w receive channel 1 rc1 81 r/w receive channel 2 rc2 82 r/w receive channel 3 rc3 83 r/w receive channel 4 rc4 84 r/w receive channel 5 rc5 85 r/w receive channel 6 rc6 86 r/w receive channel 7 rc7 87 r/w receive channel 8 rc8 88 r/w receive channel 9 rc9
DS21FT40 23 of 87 address r/w register name register abbreviation 89 r/w receive channel 10 rc10 8a r/w receive channel 11 rc11 8b r/w receive channel 12 rc12 8c r/w receive channel 13 rc13 8d r/w receive channel 14 rc14 8e r/w receive channel 15 rc15 8f r/w receive channel 16 rc16 90 r/w receive channel 17 rc17 91 r/w receive channel 18 rc18 92 r/w receive channel 19 rc19 93 r/w receive channel 20 rc20 94 r/w receive channel 21 rc21 95 r/w receive channel 22 rc22 96 r/w receive channel 23 rc23 97 r/w receive channel 24 rc24 98 r/w receive channel 25 rc25 99 r/w receive channel 26 rc26 9a r/w receive channel 27 rc27 9b r/w receive channel 28 rc28 9c r/w receive channel 29 rc29 9d r/w receive channel 30 rc30 9e r/w receive channel 31 rc31 9f r/w receive channel 32 rc32 a0 r/w transmit channel control 1 tcc1 a1 r/w transmit channel control 2 tcc2 a2 r/w transmit channel control 3 tcc3 a3 r/w transmit channel control 4 tcc4 a4 r/w receive channel control 1 rcc1 a5 r/w receive channel control 2 rcc2 a6 r/w receive channel control 3 rcc3 a7 r/w receive channel control 4 rcc4 a8 r/w common control 4 ccr4 a9 r transmit ds0 monitor tds0m aa r/w common control 5 ccr5 ab r receive ds0 monitor rds0m ac r/w test 3 test3 (set to 00h) ad ? not used (set to 00h) ae ? not used (set to 00h) af ? not used (set to 00h) b0 r/w hdlc control register hcr b1 r/w hdlc status register hsr b2 r/w hdlc interrupt mask register himr b3 r/w receive hdlc information register rhir b4 r/w receive hdlc fifo register rhfr
DS21FT40 24 of 87 address r/w register name register abbreviation b5 r/w interleave bus operation register ibo b6 r/w transmit hdlc information register thir b7 r/w transmit hdlc fifo register thfr b8 r/w receive hdlc ds0 control register 1 rdc1 b9 r/w receive hdlc ds0 control register 2 rdc2 ba r/w transmit hdlc ds0 control register 1 tdc1 bb r/w transmit hdlc ds0 control register 2 tdc2 bc ? not used (set to 00h) bd ? not used (set to 00h) be ? not used (set to 00h) bf ? not used (set to 00h) notes: 1. test registers 1, 2, and 3 are used only by the factory; these registers must be cleared (set to all zeros) on power? up initialization to insure proper operation. 2. register banks cxh, dxh, exh, and fxh are not accessible. 4. parallel port the DS21FT40 is controlled via either a non?multiplexed (mux = 0) or a multiplexed (mux = 1) bus by an external microcontroller or microprocessor. the DS21FT40 can operate with either intel or motorola bus timing configurations. if the bts pin is tied low, intel timing will be selected; if tied high, motorola timing will be selected. all motorola bus signals are listed in parenthesis (). see the timing diagrams in the a.c. electrical characteristics in section 17 for more details. 5. control, id and test registers the operation of each framer within the DS21FT40 is configured via a set of ten control registers. typically, the control registers are only accessed when the system is first powered up. once a channel in the DS21FT40 has been initialized, the control registers will only need to be accessed when there is a change in the system configuration. there are two receive control register (rcr1 and rcr2), two transmit control registers (tcr1 and tcr2), and six common control registers (ccr1 to ccr6). each of the ten registers are described in this section. there is a device identification register (idr) at address 0fh. the msb of this read?only register is fixed to a one indicating that the ds21q44 die is present. the lower 4 bits of the idr are used to display the die revision of the chip.
DS21FT40 25 of 87 power?up sequence the DS21FT40 does not automatically clear its register space on power?up. after the supplies are stable, each of the four framer?s register space should be configured for operation by writing to all of the internal registers. this includes setting the test and all unused registers to 00hex. this can be accomplished using a two-pass approach on each quad framer within the DS21FT40. 1. clear each quad framer?s register space by writing 00h to addresses 00h through 0bfh. 2. program required registers to achieve desired operating mode. finally, after the tsysclk and rsysclk inputs are stable, the esr bit should be toggled from a zero to a one (this step can be skipped if the elastic stores are disabled). idr: device identification register (address=0f hex) (msb) (lsb) t1e1 0 0 0 id3 id2 id1 id0 symbols position name and description t1e1 idr.7 t1 or e1 chip determination bit. 0=t1 chip 1=e1 chip id3 idr.3 chip revision bit 3. msb of a decimal code that represents the chip revision. id2 idr.1 chip revision bit 2. id1 idr.2 chip revision bit 1. id0 idr.0 chip revision bit 0. lsb of a decimal code that represents the chip revision. rcr1: receive control register 1 (address=10 hex) (msb) (lsb) rsmf rsm rsio ? ? frc synce resync symbols position name and description rsmf rcr1.7 rsync multiframe function. only used if the rsync pin is programmed in the multiframe mode (rcr1.6=1). 0 = rsync outputs cas multiframe boundaries 1 = rsync outputs crc4 multiframe boundaries rsm rcr1.6 rsync mode select. 0 = frame mode (see the timing in section 18) 1 = multiframe mode (see the timing in section 18) rsio rcr1.5 rsync i/o select. (note: this bit must be set to zero when rcr2.1=0). 0 = rsync is an output (depends on rcr1.6) 1 = rsync is an input (only valid if elastic store enabled) ? rcr1.4 not assigned. should be set to zero when written. ? rcr1.3 not assigned. should be set to zero when written.
DS21FT40 26 of 87 symbols position name and description frc rcr1.2 frame resync criteria. 0 = resync if fas received in error 3 consecutive times 1 = resync if fas or bit 2 of non?fas is received in error 3 consecutive times synce rcr1.1 sync enable. 0 = auto resync enabled 1 = auto resync disabled resync rcr1.0 resync. when toggled from low to high, a resync is initiated. must be cleared and set again for a subsequent resync. sync/resync criteria table 5?1 frame or multiframe level sync criteria resync criteria itu spec. fas fas present in frame n and n + 2, and fas not present in frame n + 1 three consecutive incorrect fas received alternate (rcr1.2=1) the above criteria is met or three consecutive incorrect bit 2 of non?fas received g.706 4.1.1 4.1.2 crc4 two valid mf alignment words found within 8 ms 915 or more crc4 code words out of 1000 received in error g.706 4.2 and 4.3.2 cas valid mf alignment word found and previous timeslot 16 contains code other than all zeros two consecutive mf alignment words received in error g.732 5.2 rcr2: receive control register 2 (address=11 hex) (msb) (lsb) sa8s sa7s sa6s sa5s sa4s rbcs rese ? symbols position name and description sa8s rcr2.7 sa8 bit select. not applicable for DS21FT40. sa7s rcr2.6 sa7 bit select. not applicable for DS21FT40. sa6s rcr2.5 sa6 bit select. not applicable for DS21FT40. sa5s rcr2.4 sa5 bit select. not applicable for DS21FT40. sa4s rcr2.3 sa4 bit select. not applicable for DS21FT40.
DS21FT40 27 of 87 symbols position name and description rbcs rcr2.2 receive side backplane clock select. 0 = if rsysclk is 1.544 mhz 1 = if rsysclk is 2.048 mhz rese rcr2.1 receive side elastic store enable. 0 = elastic store is bypassed 1 = elastic store is enabled ? rcr2.0 not assigned. should be set to zero when written. tcr1: transmit control register 1 (address=12 hex) (msb) (lsb) odf tfpt t16s tua1 tsis tsa1 tsm tsio symbols position name and description odf tcr1.7 output data format. 0 = bipolar data at tpos and tneg 1 = nrz data at tpos; tneg=0 tfpt tcr1.6 transmit timeslot 0 pass through. 0 = fas bits/sa bits/remote alarm sourced internally from the taf and tnaf registers 1 = fas bits/sa bits/remote alarm sourced from tser t16s tcr1.5 transmit timeslot 16 data select. 0 = sample timeslot 16 at tser pin 1 = source timeslot 16 from ts0 to ts15 registers tua1 tcr1.4 transmit unframed all ones. 0 = transmit data normally 1 = transmit an unframed all one?s code at tpos and tneg tsis tcr1.3 transmit international bit select. 0 = sample si bits at tser pin 1 = source si bits from taf and tnaf registers (in this mode, tcr1.6 must be set to 0) tsa1 tcr1.2 transmit signaling all ones. 0 = normal operation 1 = force timeslot 16 in every frame to all ones tsm cr1.1 tsync mode select. 0 = frame mode (see the timing in section 16) 1 = cas and crc4 multiframe mode (see the timing in section 16) tsio tcr1.0 tsync i/o select. 0 = tsync is an input 1 = tsync is an output note: see figure 16?15 for more details about how the transmit control registers affect the operation of the DS21FT40.
DS21FT40 28 of 87 tcr2: transmit control register 2 (address=13 hex) (msb) (lsb) sa8s sa7s sa6s sa5s sa4s odm aebe pf symbols position name and description sa8s tcr2.7 sa8 bit select. not applicable for DS21FT40. sa7s tcr2.6 sa7 bit select. not applicable for DS21FT40. sa6s tcr2.5 sa6 bit select. not applicable for DS21FT40. sa5s tcr2.4 sa5 bit select. not applicable for DS21FT40. sa4s tcr2.3 sa4 bit select. not applicable for DS21FT40. odm tcr2.2 output data mode. 0 = pulses at tposo and tnego are one full tclko period wide 1 = pulses at tposo and tnego are 1/2 tclko period wide aebe tcr2.1 automatic e?bit enable. 0 = e?bits not automatically set in the transmit direction 1 = e?bits automatically set in the transmit direction pf tcr2.0 function of rlos/lotc pin. not applicable for DS21FT40. should be cleared to zero. ccr1: common control register 1 (address=14 hex) (msb) (lsb) flb thdb3 tg802 tcrc4 rsm rhdb3 rg802 rcrc4 symbols position name and description flb ccr1.7 framer loopback. 0=loopback disabled 1=loopback enabled thdb3 ccr1.6 transmit hdb3 enable. 0=hdb3 disabled 1=hdb3 enabled tg802 ccr1.5 transmit g.802 enable. see section 16 for details. not applicable for DS21FT40. should be cleared to zero. tcrc4 ccr1.4 transmit crc4 enable. 0=crc4 disabled 1=crc4 enabled rsm ccr1.3 receive signaling mode select. 0=cas signaling mode 1=ccs signaling mode rhdb3 ccr1.2 receive hdb3 enable. 0=hdb3 disabled 1=hdb3 enabled
DS21FT40 29 of 87 symbols position name and description rg802 ccr1.1 receive g.802 enable. see section 16 for details. not applicable for DS21FT40. should be cleared to zero. rcrc4 ccr1.0 receive crc4 enable. 0=crc4 disabled 1=crc4 enabled framer loopback when ccr1.7 is set to a one, the framer will enter a framer loopback (flb) mode. see figure 1?2 for more details. this loopback is useful in testing and debugging applications. in flb, the framer will loop data from the transmit side back to the receive side. when flb is enabled, the following will occur: 1. data will be transmitted as normal at tpos and tneg. 2. data input via rpos and rneg will be ignored. 3. the rclk output will be replaced with the tclk input. ccr2: common control register 2 (address=1a hex) (msb) (lsb) ecus vcrfs aais ara rserc lotcmc rff rfe symbols position name and description ecus ccr2.7 error counter update select. see section 7 for details. 0=update error counters once a second 1=update error counters every 62.5 ms (500 frames) vcrfs ccr2.6 vcr function select. see section 7 for details. 0=count bipolar violations (bpvs) 1=count code violations (cvs) aais ccr2.5 automatic ais generation. 0=disabled 1=enabled ara ccr2.4 automatic remote alarm generation. 0=disabled 1=enabled rserc ccr2.3 rser control. 0=allow rser to output data as received under all conditions 1=force rser to one under loss of frame alignment conditions lotcmc ccr2.2 loss of transmit clock mux control. determines whether the transmit side formatter should switch to the ever present rclk if the tclk should fail to transition (see figure 1?2). 0=do not switch to rclk if tclk stops 1=switch to rclk if tclk stops rff ccr2.1 receive force freeze. freezes receive side signaling at rser (if ccr3.3=1); will override receive freeze enable (rfe). see section 9 for details. 0=do not force a freeze event 1=force a freeze event
DS21FT40 30 of 87 symbols position name and description rfe ccr2.0 receive freeze enable. see section 9 for details. 0=no freezing of receive signaling data will occur 1=allow freezing of receive signaling data at rser (if ccr3.3=1). automatic alarm generation the DS21FT40 can be programmed to automatically transmit ais or remote alarm. when automatic ais generation is enabled (ccr2.5 = 1), the framer monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, ais alarm (all one?s) reception, or loss of receive carrier (or signal). if any one (or more) of the above conditions is present, then the framer will transmit an ais alarm. when automatic rai generation is enabled (ccr2.4 = 1), the framer monitors the receive side to determine if any of the following conditions are present: loss of receive frame synchronization, ais alarm (all one?s) reception, loss of receive carrier or if crc4 multiframe synchronization (if enabled) cannot be found within 128 ms of fas synchronization. if any one (or more) of the above conditions is present, then the framer will transmit a rai alarm. rai generation conforms to ets 300 011 specifications and a constant remote alarm will be transmitted if the framer cannot find crc4 multiframe synchronization within 400 ms as per g.706. it is an illegal state to have both ccr2.4 and ccr2.5 set to one at the same time. ccr3: common control register 3 (address=1b hex) (msb) (lsb) tese tcbfs tirfs ? rsre thse tbcs rcla symbols position name and description tese ccr3.7 transmit side elastic store enable. 0=elastic store is bypassed 1=elastic store is enabled tcbfs ccr3.6 transmit channel blocking registers (tcbr) function select. 0=tcbrs define the operation of the tchblk output pin (not applicable for DS21FT40) 1=tcbrs define which signaling bits are to be inserted tirfs ccr3.5 transmit idle registers (tir) function select. see section 10 for details. 0=tirs define in which channels to insert idle code 1=tirs define in which channels to insert data from rser (i.e., per channel loopback function) ? ccr3.4 not assigned. should be set to zero when written.
DS21FT40 31 of 87 symbols position name and description rsre ccr3.3 receive side signaling re?insertion enable. see section 9 for details. 0=do not re?insert signaling bits into the data stream presented at the rser pin 1=re?insert the signaling bits into data stream presented at the rser pin thse ccr3.2 transmit side hardware signaling insertion enable. not applicable for DS21FT40. should be cleared to zero. tbcs ccr3.1 transmit side backplane clock select. 0=if tsysclk is 1.544 mhz 1=if tsysclk is 2.048 mhz rcla ccr3.0 receive carrier loss (rcl) alternate criteria. 0=rcl declared upon 255 consecutive zeros (125 us) 1=rcl declared upon 2048 consecutive zeros (1 ms) ccr4: common control register 4 (address=a8 hex) (msb) (lsb) rlb ? ? tcm4 tcm3 tcm2 tcm1 tcm0 symbols position name and description rlb ccr4.7 remote loopback. 0 = loopback disabled 1 = loopback enabled ? ccr4.6 not assigned. should be set to zero when written. ? ccr4.5 not assigned. should be set to zero when written. tcm4 ccr4.4 transmit channel monitor bit 4. msb of a channel decode that deter-mines which transmit channel data will appear in the tds0m register. see section 8 for details. tcm3 ccr4.3 transmit channel monitor bit 3. tcm2 ccr4.2 transmit channel monitor bit 2. tcm1 ccr4.1 transmit channel monitor bit 1. tcm0 ccr4.0 transmit channel monitor bit 0. lsb of the channel decode.
DS21FT40 32 of 87 ccr5: common control register 5 (address = aa hex) (msb) (lsb) ? resalgn tesalgn rcm4 rcm3 rcm2 rcm1 rcm0 symbols position name and description ? ccr5.7 not assigned. should be set to zero when written resalgn ccr5.6 receive elastic store align. setting this bit from a zero to a one may force the receive elastic store?s write/read pointers to a minimum separation of half a frame. no action will be taken if the pointer separation is already greater or equal to half a frame. if pointer separation is less then half a frame, the command will be executed and data will be disrupted. should be toggled after rsysclk has been applied and is stable. must be cleared and set again for a subsequent align. see section 12 for details. tesalgn ccr5.5 transmit elastic store align. setting this bit from a zero to a one may force the transmit elastic store?s write/read pointers to a minimum separation of half a frame. no action will be taken if the pointer separation is already greater or equal to half a frame. if pointer separation is less then half a frame, the command will be executed and data will be disrupted. should be toggled after tsysclk has been applied and is stable. must be cleared and set again for a subsequent align. see section 12 for details. rcm4 ccr5.4 receive channel monitor bit 4. msb of a channel decode that determines which receive channel data will appear in the rds0m register. see section 8 for details. rcm3 ccr5.3 receive channel monitor bit 3. rcm2 ccr5.2 receive channel monitor bit 2. rcm1 ccr5.1 receive channel monitor bit 1. rcm0 ccr5.0 receive channel monitor bit 0. lsb of the channel decode. ccr6: common control register 6 (address=1d hex) (msb) (lsb) ? ? ? ? ? tclksrc resr tesr symbols position name and description ? ccr6.7 not assigned. should be set to zero when written ? ccr6.6 not assigned. should be set to zero when written ? ccr6.5 not assigned. should be set to zero when written ? ccr6.4 not assigned. should be set to zero when written ? ccr6.3 not assigned. should be set to zero when written
DS21FT40 33 of 87 symbols position name and description tclksrc ccr6.2 transmit clock source select. this function allows the user to internally select rclk as the clock source for the transmit side formatter. 0 = transmit side formatter clocked with signal applied at tclk pin. lotc mux function is operational (tcr1.7) 1 = transmit side formatter clocked with rclk. resr ccr6.1 receive elastic store reset. setting this bit from a zero to a one will force the receive elastic store to a depth of one frame. receive data is lost during the reset. should be toggled after rsysclk has been applied and is stable. do not leave this bit set high. tesr ccr6.0 transmit elastic store reset. setting this bit from a zero to a one will force the transmit elastic store to a depth of one frame. transmit data is lost during the reset. should be toggled after tsysclk has been applied and is stable. do not leave this bit set high. 6. status and information registers there is a set of seven registers per framer that contain information on the current real time status of a framer in the DS21FT40, status register 1 (sr1), status register 2 (sr2), receive information register (rir), synchronizer status register (ssr) and a set of three registers for the onboard hdlc controller. the specific details on the four registers pertaining to the hdlc controller are covered in section 14 but they operate the same as the other status registers in the DS21FT40 and this operation is described below. when a particular event has occurred (or is occurring), the appropriate bit in one of these four registers will be set to a one. all of the bits in sr1, sr2, and rir1 registers operate in a latched fashion. the synchronizer status register contents are not latched. this means that if an event or an alarm occurs and a bit is set to a one in any of the registers, it will remain set until the user reads that bit. the bit will be cleared when it is read and it will not be set again until the event has occurred again (or in the case of the rsa1, rsa0, rdma, rua1, rra, rcl, and rlos alarms, the bit will remain set if the alarm is still present). the user will always precede a read of any of the sr1, sr2 and rir registers with a write. the byte written to the register will inform the framer which bits the user wishes to read and have cleared. the user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. when a one is written to a bit location, the read register will be updated with the latest information. when a zero is written to a bit position, the read register will not be updated and the previous value will be held. a write to the status and information registers will be immediately followed by a read of the same register. the read result should be logically and?ed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. this second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. this write?read? write scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. this operation is key in controlling the DS21FT40 with higher?order software languages.
DS21FT40 34 of 87 the ssr register operates differently than the other three. it is a read only register and it reports the status of the synchronizer in real time. this register is not latched and it is not necessary to precede a read of this register with a write. the sr1, sr2, and hsr registers have the unique ability to initiate a hardware interrupt via the int* output pin. each of the alarms and events in the sr1, sr2, and hsr can be either masked or unmasked from the interrupt pin via the interrupt mask register 1 (imr1), interrupt mask register 2 (imr2), and hdlc interrupt mask register (himr) respectively. the himr register is covered in section 14. the interrupts caused by four of the alarms in sr1 (namely rua1, rra, rcl, and rlos) act differently than the interrupts caused by other alarms and events in sr1 and sr2 (namely rsa1, rdma, rsa0, rslip, rmf, raf, tmf, sec, taf, lotc, rcmf, and tslip). these four alarm interrupts will force the int* pin low whenever the alarm changes state (i.e., the alarm goes active or inactive according to the set/clear criteria in table 6-1). the int* pin will be allowed to return high (if no other interrupts are present) when the user reads the alarm bit that caused the interrupt to occur. if the alarm is still present, the register bit will remain set. the event caused interrupts will force the int* pin low when the event occurs. the int* pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. isr: interrupt status register (any address from 0c0 hex to 0ff hex) (msb) (lsb) f3hdlc f3sr f2hdlc f2sr f1hdlc f1sr f0hdlc f0sr symbols position name and description f3hdlc isr.7 framer 3 hdlc controller interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. f3sr isr.6 framer 3 sr1 or sr2 interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. f2hdlc isr.5 framer 2 hdlc controller interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. f2sr isr.4 framer 2 sr1 or sr2 interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. f1hdlc isr.3 framer 1 hdlc controller interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. f1sr isr.2 framer 1 sr1 or sr2 interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. f0hdlc isr.1 framer 0 hdlc controller interrupt request. 0 = no interrupt request pending.
DS21FT40 35 of 87 symbols position name and description 1 = interrupt request pending. f0sr isr.0 framer 0 sr1 or sr2 interrupt request. 0 = no interrupt request pending. 1 = interrupt request pending. rir: receive information register (address=08 hex) (msb) (lsb) tesf tese ? resf rese crcrc fasrc casrc symbols position name and description tesf rir.7 transmit side elastic store full. set when the transmit side elastic store buffer fills and a frame is deleted. tese rir.6 transmit side elastic store empty. set when the transmit side elastic store buffer empties and a frame is repeated. ? rir.5 not assigned. could be any value. resf rir.4 receive side elastic store full. set when the receive side elastic store buffer fills and a frame is deleted. rese rir.3 receive side elastic store empty. set when the receive side elastic store buffer empties and a frame is repeated. crcrc rir.2 crc resync criteria met. set when 915/1000 code words are received in error. fasrc rir.1 fas resync criteria met. set when 3 consecutive fas words are received in error. casrc rir.0 cas resync criteria met. set when 2 consecutive cas mf alignment words are received in error. ssr: synchronizer status register (address=1e hex) (msb) (lsb) csc5 csc4 csc3 csc2 csc0 fassa cassa crc4sa symbols position name and description csc5 ssr.7 crc4 sync counter bit 5. msb of the 6?bit counter. csc4 ssr.6 crc4 sync counter bit 4. csc3 ssr.5 crc4 sync counter bit 3. csc2 ssr.4 crc4 sync counter bit 2. csc0 ssr.3 crc4 sync counter bit 0. lsb of the 6?bit counter. the next to lsb is not accessible. fassa ssr.2 fas sync active. set while the synchronizer is searching for alignment at the fas level. cassa ssr.1 cas mf sync active. set while the synchronizer is searching for the cas mf alignment word. crc4sa ssr.0 crc4 mf sync active. set while the synchronizer is searching for the crc4 mf alignment word.
DS21FT40 36 of 87 crc4 sync counter the crc4 sync counter increments each time the 8 ms crc4 multiframe search times out. the counter is cleared when the framer has successfully obtained synchronization at the crc4 level. the counter can also be cleared by disabling the crc4 mode (ccr1.0=0). this counter is useful for determining the amount of time the framer has been searching for synchronization at the crc4 level. itu g.706 suggests that if synchronization at the crc4 level cannot be obtained within 400 ms, then the search should be abandoned and proper action taken. the crc4 sync counter will rollover. sr1: status register 1 (address=06 hex) (msb) (lsb) rsa1 rdma rsa0 rslip rua1 rra rcl rlos symbols position name and description rsa1 sr1.7 receive signaling all ones / signaling change. set when over a full mf, the content of timeslot 16 contains less than three zeros. this alarm is not disabled in the ccs signaling mode. a change in the contents of rs1 through rs16 from one multiframe to the next will cause rsa1 and rsa0 to be set. rdma sr1.6 receive distant mf alarm. set when bit?6 of timeslot 16 in frame 0 has been set for two consecutive multiframes. this alarm is not disabled in the ccs signaling mode. rsa0 sr1.5 receive signaling all zeros / signaling change. set when over a full mf, timeslot 16 contains all zeros. a change in the contents of rs1 through rs16 from one multiframe to the next will cause rsa1 and rsa0 to be set. rslip sr1.4 receive side elastic store slip. set when the elastic store has either repeated or deleted a frame of data. rua1 sr1.3 receive unframed all ones. set when an unframed all ones code is received at rpos and rneg. rra sr1.2 receive remote alarm. set when a remote alarm is received at rpos and rneg. rcl sr1.1 receive carrier loss. set when 255 (or 2048 if ccr3.0=1) consecutive zeros have been detected at rpos and rneg. rlos sr1.0 receive loss of sync. set when the device is not synchronized to the receive e1 stream.
DS21FT40 37 of 87 alarm criteria table 6-1 alarm set criteria clear criteria itu spec. rsa1 (receive signaling all ones) over 16 consecutive frames (one full mf) timeslot 16 contains less than three zeros over 16 consecutive frames (one full mf) timeslot 16 contains three or more zeros g.732 4.2 rsa0 (receive signaling all zeros) over 16 consecutive frames (one full mf) timeslot 16 contains all zeros over 16 consecutive frames (one full mf) timeslot 16 contains at least a single one g.732 5.2 rdma (receive distant multiframe alarm) bit 6 in timeslot 16 of frame 0 set to one for two consecutive mf bit 6 in timeslot 16 of frame 0 set to zero for two consecutive mf o.162 2.1.5 rua1 (receive unframed all ones) less than three zeros in two frames (512 bits) more than two zeros in two frames (512 bits) o.162 1.6.1.2 rra (receive remote alarm) bit 3 of non?align frame set to one for three consecutive occasions bit 3 of non?align frame set to zero for three consecutive occasions o.162 2.1.4 rcl (receive carrier loss) 255 (or 2048) consecutive zeros received in 255 bit times, at least 32 ones are received g.775 / g.962 sr2: status register 2 (address=07 hex) (msb) (lsb) rmf raf tmf sec taf lotc rcmf tslip symbols position name and description rmf sr2.7 receive cas multiframe. set every 2 ms (regardless if cas signaling is enabled or not) on receive multiframe boundaries. used to alert the host that signaling data is available. raf sr2.6 receive align frame. set every 250 s at the beginning of align frames. used to alert the host that si and sa bits are available in the raf and rnaf registers. tmf sr2.5 transmit multiframe. set every 2 ms (regardless if crc4 is enabled) on transmit multiframe boundaries. used to alert the host that signaling data needs to be updated. sec sr2.4 one second timer. set on increments of one second based on rclk. if ccr2.7=1, then this bit will be set every 62.5 ms instead of once a second. taf sr2.3 transmit align frame. set every 250 s at the beginning of align frames. used to alert the host that the taf and tnaf registers need to be updated.
DS21FT40 38 of 87 symbols position name and description lotc sr2.2 loss of transmit clock. set when the tclk pin has not transitioned for one channel time (or 3.9 s). rcmf sr2.1 receive crc4 multiframe. set on crc4 multiframe boundaries; will continue to be set every 2 ms on an arbitrary boundary if crc4 is disabled. tslip sr2.0 transmit elastic store slip. set when the elastic store has either repeated or deleted a frame of data. imr1: interrupt mask register 1 (address=16 hex) (msb) (lsb) rsa1 rdma rsa0 rslip rua1 rra rcl rlos symbols position name and description rsa1 imr1.7 receive signaling all ones / signaling change. 0=interrupt masked 1=interrupt enabled rdma imr1.6 receive distant mf alarm. 0=interrupt masked 1=interrupt enabled rsa0 imr1.5 receive signaling all zeros / signaling change. 0=interrupt masked 1=interrupt enabled rslip imr1.4 receive elastic store slip occurrence. 0=interrupt masked 1=interrupt enabled rua1 imr1.3 receive unframed all ones. 0=interrupt masked 1=interrupt enabled rra imr1.2 receive remote alarm. 0=interrupt masked 1=interrupt enabled rcl imr1.1 receive carrier loss. 0=interrupt masked 1=interrupt enabled rlos imr1.0 receive loss of sync. 0=interrupt masked 1=interrupt enabled
DS21FT40 39 of 87 imr2: interrupt mask register 2 (address=17 hex) (msb) (lsb) rmf raf tmf sec taf lotc rcmf tslip symbols position name and description rmf imr2.7 receive cas multiframe. 0=interrupt masked 1=interrupt enabled raf imr2.6 receive align frame. 0=interrupt masked 1=interrupt enabled tmf imr2.5 transmit multiframe. 0=interrupt masked 1=interrupt enabled sec imr2.4 one second timer. 0=interrupt masked 1=interrupt enabled taf imr2.3 transmit align frame. 0=interrupt masked 1=interrupt enabled lotc imr2.2 loss of transmit clock. 0=interrupt masked 1=interrupt enabled rcmf imr2.1 receive crc4 multiframe. 0=interrupt masked 1=interrupt enabled tslip imr2.0 transmit side elastic store slip occurrence. 0=interrupt masked 1=interrupt enabled 7. error count registers there are a set of four counters in each framer that record bipolar or code violations, errors in the crc4 smf code words, e bits as reported by the far end, and word errors in the fas. each of these four counters are automatically updated on either one second boundaries (ccr2.7=0) or every 62.5 ms (ccr2.7=1) as determined by the timer in status register 2 (sr2.4). hence, these registers contain performance data from either the previous second or the previous 62.5 ms. the user can use the interrupt from the one second timer to determine when to read these registers. the user has a full second (or 62.5 ms) to read the counters before the data is lost. all four counters will saturate at their respective maximum counts and they will not rollover. bpv or code violation counter violation count register 1 (vcr1) is the most significant word and vcr2 is the least significant word of a 16?bit counter that records either bipolar violations (bpvs) or code violations (cvs). if ccr2.6=0, then the vcr counts bipolar violations. bipolar violations are defined as consecutive marks of the same polarity. in this mode, if the hdb3 mode is set for the receive side via ccr1.2, then hdb3 code words are not counted as bpvs. if ccr2.6=1, then the vcr counts code violations as defined in itu o.161. code violations are defined as consecutive bipolar violations of the same polarity. in most applications,
DS21FT40 40 of 87 the framer should be programmed to count bpvs when receiving ami code and to count cvs when receiving hdb3 code. this counter increments at all times and is not disabled by loss of sync conditions. the counter saturates at 65,535 and will not rollover. the bit error rate on a e1 line would have to be greater than 10** ?2 before the vcr would saturate. vcr1: upper bipolar violation count register 1 (address=00 hex) vcr2: lower bipolar violation count register 2 (address=01 hex) (msb) (lsb) v15 v14 v13 v12 v11 v10 v9 v8 vcr1 v7 v6 v5 v4 v3 v2 v1 v0 vcr2 symbols position name and description v15 vcr1.7 msb of the 16?bit code violation count v0 vcr2.0 lsb of the 10?bit code violation count crc4 error counter crc4 count register 1 (crccr1) is the most significant word and crccr2 is the least significant word of a 10?bit counter that records word errors in the cyclic redundancy check 4 (crc4). since the maximum crc4 count in a one second period is 1000, this counter cannot saturate. the counter is disabled during loss of sync at either the fas or crc4 level; it will continue to count if loss of multiframe sync occurs at the cas level. crccr1: crc4 count register 1 (address=02 hex) crccr2: crc4 count register 2 (address=03 hex) (msb) (lsb) (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) crc9 crc8 crccr1 crc7 crc6 crc5 crc4 crc3 crc2 crc1 crc0 crccr2 symbols position name and description crc9 crccr1.1 msb of the 10?bit crc4 error count crc0 crccr2.0 lsb of the 10?bit crc4 error count note: 1. the upper 6 bits of crccr1 at address 02 are the most significant bits of the 12?bit fas error counter. e?bit counter e?bit count register 1 (ebcr1) is the most significant word and ebcr2 is the least significant word of a 10?bit counter that records far end block errors (febe) as reported in the first bit of frames 13 and 15 on e1 lines running with crc4 multiframe. these count registers will increment once each time the received e?bit is set to zero. since the maximum e?bit count in a one second period is 1000, this counter cannot saturate. the counter is disabled during loss of sync at either the fas or crc4 level; it will continue to count if loss of multiframe sync occurs at the cas level.
DS21FT40 41 of 87 ebcr1: e?bit count register 1 (address=04 hex) ebcr2: e?bit count register 2 (address=05 hex) (msb) (lsb) (note 1) (note 1) (note 1) (note 1) (note 1) (note 1) eb9 eb8 ebcr1 eb7 eb6 eb5 eb4 eb3 eb2 eb1 eb0 ebcr2 symbols position name and description eb9 ebcr1.1 msb of the 10?bit e?bit error count eb0 ebcr2.0 lsb of the 10?bit e?bit error count note: the upper 6 bits of ebcr1 at address 04 are the least significant bits of the 12?bit fas error counter. fas error counter fas count register 1 (fascr1) is the most significant word and fascr2 is the least significant word of a 12?bit counter that records word errors in the frame alignment signal in timeslot 0. this counter is disabled when rlos is high. fas errors will not be counted when the framer is searching for fas alignment and/or synchronization at either the cas or crc4 multiframe level. since the maximum fas word error count in a one second period is 4000, this counter cannot saturate. fascr1: fas error count register 1 (address=02 hex) fascr2: fas error count register 2 (address=04 hex) (msb) (lsb) fas11 fas10 fas9 fas8 fas7 fas6 (note 2) (note 2) fascr1 fas5 fas4 fas3 fas2 fas1 fas0 (note 1) (note 1) fascr2 symbols position name and description fas11 fascr1.7 msb of the 12?bit fas error count fas0 fascr2.2 lsb of the 12?bit fas error count notes: 1. the lower 2 bits of fascr1 at address 02 are the most significant bits of the 10?bit crc4 error counter. 2. the lower 2 bits of fascr2 at address 04 are the most significant bits of the 10?bit e?bit counter. 8. ds0 monitoring function each framer in the DS21FT40 has the ability to monitor one ds0 64kbps channel in the transmit direction and one ds0 channel in the receive direction at the same time. in the transmit direction the user will determine which channel is to be monitored by properly setting the tcm0 to tcm4 bits in the ccr4 register. in the receive direction, the rcm0 to rcm4 bits in the ccr5 register need to be properly set. the ds0 channel pointed to by the tcm0 to tcm4 bits will appear in the transmit ds0 monitor (tds0m) register and the ds0 channel pointed to by the rcm0 to rcm4 bits will appear in the receive ds0 (rds0m) register. the tcm4 to tcm0 and rcm4 to rcm0 bits should be programmed with the decimal decode of the appropriate e1 channel. for example, if ds0 channel 6 (timeslot 5) in the transmit
DS21FT40 42 of 87 direction and ds0 channel 15 (timeslot 14) in the receive direction needed to be monitored, then the following values would be programmed into ccr4 and ccr5: tcm4 = 0 rcm4 = 0 tcm3 = 0 rcm3 = 1 tcm2 = 1 rcm2 = 1 tcm1 = 0 rcm1 = 1 tcm0 = 1 rcm0 = 0 ccr4: common control register 4 (address=a8 hex) [repeated here from section 5 for convenience] (msb) (lsb) rlb ? ? tcm4 tcm3 tcm2 tcm1 tcm0 symbols position name and description rlb ccr4.7 remote loopback. 0 = loopback disabled 1 = loopback enabled ? ccr4.6 not assigned. should be set to zero when written. ? ccr4.5 not assigned. should be set to zero when written. tcm4 ccr4.4 transmit channel monitor bit 4. msb of a channel decode that deter-mines which transmit channel data will appear in the tds0m register. see section 8 or details. tcm3 ccr4.3 transmit channel monitor bit 3. tcm2 ccr4.2 transmit channel monitor bit 2. tcm1 ccr4.1 transmit channel monitor bit 1. tcm0 ccr4.0 transmit channel monitor bit 0. lsb of the channel decode. tds0m: transmit ds0 monitor register (address=a9 hex) (msb) (lsb) b1 b2 b3 b4 b5 b6 b7 b8 symbols position name and description b1 tds0m.7 transmit ds0 channel bit 1. msb of the ds0 channel (first bit to be transmitted). b2 tds0m.6 transmit ds0 channel bit 2. b3 tds0m.5 transmit ds0 channel bit 3. b4 tds0m.4 transmit ds0 channel bit 4. b5 tds0m.3 transmit ds0 channel bit 5. b6 tds0m.2 transmit ds0 channel bit 6. b7 tds0m.1 transmit ds0 channel bit 7. b8 tds0m.0 transmit ds0 channel bit 8. lsb of the ds0 channel (last bit to be transmitted).
DS21FT40 43 of 87 ccr5: common control register 5 (address=aa hex) [repeated here from section 5 for convenience] (msb) (lsb) ? resalgn tesalgn rcm4 rcm3 rcm2 rcm1 rcm0 symbols position name and description ? ccr5.7 not assigned. should be set to zero when written resalgn ccr5.6 receive elastic store align. setting this bit from a zero to a one may force the receive elastic store?s write/read pointers to a minimum separation of half a frame. no action will be taken if the pointer separation is already greater or equal to half a frame. if pointer separation is less then half a frame, the command will be executed and data will be disrupted. should be toggled after rsysclk has been applied and is stable. must be cleared and set again for a subsequent align. see section 12 for details. tesalgn ccr5.5 transmit elastic store align. setting this bit from a zero to a one may force the transmit elastic store?s write/read pointers to a minimum separation of half a frame. no action will be taken if the pointer separation is already greater or equal to half a frame. if pointer separation is less then half a frame, the command will be executed and data will be disrupted. should be toggled after tsysclk has been applied and is stable. must be cleared and set again for a subsequent align. see section 12 for details. rcm4 ccr5.4 receive channel monitor bit 4. msb of a channel decode that determines which receive channel data will appear in the rds0m register. see section 8 for details. rcm3 ccr5.3 receive channel monitor bit 3. rcm2 ccr5.2 receive channel monitor bit 2. rcm1 ccr5.1 receive channel monitor bit 1. rcm0 ccr5.0 receive channel monitor bit 0. lsb of the channel decode.
DS21FT40 44 of 87 rds0m: receive ds0 monitor register (address = ab hex) (msb) (lsb) b1 b2 b3 b4 b5 b6 b7 b8 symbols position name and description b1 rds0m.7 receive ds0 channel bit 1. msb of the ds0 channel (first bit to be received). b2 rds0m.6 receive ds0 channel bit 2. b3 rds0m.5 receive ds0 channel bit 3. b4 rds0m.4 receive ds0 channel bit 4. b5 rds0m.3 receive ds0 channel bit 5. b6 rds0m.2 receive ds0 channel bit 6. b7 rds0m.1 receive ds0 channel bit 7. b8 rds0m.0 receive ds0 channel bit 8. lsb of the ds0 channel (last bit to be received). 9. signaling operation each framer in the DS21FT40 contains provisions for both processor based (i.e., software based) signaling bit access and for hardware based access. both the processor based access and the hardware based access can be used simultaneously if necessary. the processor based signaling is covered in section 9.1 and the hardware based signaling is covered in section 9.2. 9.1 processor based signaling the channel associated signaling (cas) bits embedded in the e1 stream can be extracted from the receive stream and inserted into the transmit stream by the framer. each of the 30 voice channels has four signaling bits (a/b/c/d) associated with it. the numbers in parenthesis () are the voice channel associated with a particular signaling bit. the voice channel numbers have been assigned as described in the itu documents. please note that this is different than the channel numbering scheme (1 to 32) that is used in the rest of the data sheet. for example, voice channel 1 is associated with timeslot 1 (channel 2) and voice channel 30 is associated with timeslot 31 (channel 32). there is a set of 16 registers for the receive side (rs1 to rs16) and 16 registers on the transmit side (ts1 to ts16). the signaling registers are detailed below.
DS21FT40 45 of 87 rs1 to rs16: receive signaling registers (address=30 to 3f hex) (msb) (lsb) 0 0 0 0 x y x x rs1 (30) a(1) b(1) c(1) d(1) a(16) b(16) c(16) d(16) rs2 (31) a(2) b(2) c(2) d(2) a(17) b(17) c(17) d(17) rs3 (32) a(3) b(3) c(3) d(3) a(18) b(18) c(18) d(18) rs3 (33) a(4) b(4) c(4) d(4) a(19) b(19) c(19) d(19) rs5 (34) a(5) b(5) c(5) d(5) a(20) b(20) c(20) d(20) rs6 (35) a(6) b(6) c(6) d(6) a(21) b(21) c(21) d(21) rs7 (36) a(7) b(7) b(7) b(7) b(22) b(22) b(22) b(22) rs8 (37) a(8) b(8) c(8) d(8) a(23) b(23) c(23) d(23) rs9 (38) a(9) b(9) c(9) d(9) a(24) b(24) c(24) d(24) rs10 (39) a(10) b(10) c(10) d(10) a(25) b(25) c(25) d(25) rs11 (3a) a(11) b(11) c(11) d(11) a(26) b(26) c(26) d(26) rs12 (3b) a(12) b(12) c(12) d(12) a(27) b(27) c(27) d(27) rs13 (3c) a(13) b(13) c(13) d(13) a(28) b(28) c(28) d(28) rs14 (3d) a(14) b(14) c(14) d(14) a(29) b(29) c(29) d(29) rs15 (3e) a(15) b(15) c(15) d(15) a(30) b(30) c(30) d(30) rs16 (3f) symbols position name and description x rs1.0/1/3 spare bits. y rs1.2 remote alarm bit (integrated and reported in sr1.6). a(1) rs2.7 signaling bit a for channel 1 d(30) rs16.0 signaling bit d for channel 30. each receive signaling register (rs1 to rs16) reports the incoming signaling from two timeslots. the bits in the receive signaling registers are updated on multiframe boundaries so the user can utilize the receive multiframe interrupt in the receive status register 2 (sr2.7) to know when to retrieve the signaling bits. the user has a full 2 ms to retrieve the signaling bits before the data is lost. the rs registers are updated under all conditions. their validity should be qualified by checking for synchronization at the cas level. in ccs signaling mode, rs1 to rs16 can also be used to extract signaling information. via the sr2.7 bit, the user will be informed when the signaling registers have been loaded with data. the user has 2 ms to retrieve the data before it is lost. the signaling data reported in rs1 to rs16 is also available at the rser pin. three status bits in status register 1 (sr1) monitor the contents of registers rs1 through rs16. status monitored includes all zeros detection, all ones detection and a change in register contents. the receive signaling all zeros status bit (sr1.5) is set when over a full multi-frame, rs1 through rs16 contain all zeros. the receive signaling all ones status bit (sr1.7) is set when over a full multi-frame, rs1 through rs16 contain less than three zeros. a change in the contents of rs1 through rs16 from one multiframe to the next will cause rsa1 (sr1.7) and rsa0 (sr1.5) status bits to be set at the same time. the user can enable the int* pin to toggle low upon detection of a change in signaling by setting either the imr1.7 or imr1.5 bit. once a signaling change has been detected, the user has at least 1.75 ms to read the data out of the rs1 to rs16 registers before the data will be lost.
DS21FT40 46 of 87 ts1 to ts16: transmit signaling registers (address=40 to 4f hex) (msb) (lsb) 0000 xyxxts1 (40) a(1) b(1) c(1) d(1) a(16) b(16) c(16) d(16) ts2 (41) a(2) b(2) c(2) d(2) a(17) b(17) c(17) d(17) ts3 (42) a(3) b(3) c(3) d(3) a(18) b(18) c(18) d(18) ts4 (43) a(4) b(4) c(4) d(4) a(19) b(19) c(19) d(19) ts5 (44) a(5) b(5) c(5) d(5) a(20) b(20) c(20) d(20) ts6 (45) a(6) b(6) c(6) d(6) a(21) b(21) c(21) d(21) ts7 (46) a(7) b(7) b(7) b(7) b(22) b(22) b(22) b(22) ts8 (47) a(8) b(8) c(8) d(8) a(23) b(23) c(23) d(23) ts9 (48) a(9) b(9) c(9) d(9) a(24) b(24) c(24) d(24) ts10 (49) a(10) b(10) c(10) d(10) a(25) b(25) c(25) d(25) ts11 (4a) a(11) b(11) c(11) d(11) a(26) b(26) c(26) d(26) ts12 (4b) a(12) b(12) c(12) d(12) a(27) b(27) c(27) d(27) ts13 (4c) a(13) b(13) c(13) d(13) a(28) b(28) c(28) d(28) ts14 (4d) a(14) b(14) c(14) d(14) a(29) b(29) c(29) d(29) ts15 (4e) a(15) b(15) c(15) d(15) a(30) b(30) c(30) d(30) ts16 (4f) symbols position name and description x ts1.0/1/3 spare bits. y ts1.2 remote alarm bit (integrated and reported in sr1.6). a(1) ts2.7 signaling bit a for channel 1 d(30) ts16.0 signaling bit d for channel 30. each transmit signaling register (ts1 to ts16) contains the cas bits for two timeslots that will be inserted into the outgoing stream if enabled to do so via tcr1.5. on multiframe boundaries, the framer will load the values present in the transmit signaling register into an outgoing signaling shift register that is internal to the device. the user can utilize the transmit multiframe bit in status register 2 (sr2.5) to know when to update the signaling bits. the bit will be set every 2 ms and the user has 2 ms to update the tsr?s before the old data will be retransmitted. itu specifications recommend that the abcd signaling not be set to all zeros because they will emulate a cas multiframe alignment word. the ts1 register is special because it contains the cas multiframe alignment word in its upper nibble. the upper nibble must always be set to 0000 or else the terminal at the far end will lose multiframe synchronization. if the user wishes to transmit a multiframe alarm to the far end, then the ts1.2 bit should be set to a one. if no alarm is to be transmitted, then the ts1.2 bit should be cleared. the three remaining bits in ts1 are the spare bits. if they are not used, they should be set to one. in ccs signaling mode, ts1 to ts16 can also be used to insert signaling information. via the sr2.5 bit, the user will be informed when the signaling registers need to be loaded with data. the user has 2 ms to load the data before the old data will be retransmitted. via the ccr3.6 bit, the user has the option to use the transmit channel blocking registers (tcbrs) to determine on a channel by channel basis, which signaling bits are to be inserted via the tsrs (the corresponding bit in the tcbrs=1) and which are to be sourced from the tser pin. see the transmit data flow diagram in section 16 for more details.
DS21FT40 47 of 87 tcbr1/tcbr2/tcbr3/tcbr4: definition when ccr3.6=1 (msb) (lsb) ch20 ch4 ch19 ch3 ch18 ch2 ch17* ch1* tcbr1(22) ch24 ch8 ch23 ch7 ch22 ch6 ch21 ch5 tcbr2(23) ch28 ch12 ch27 ch11 ch26 ch10 ch25 ch9 tcbr3(24) ch32 ch16 ch31 ch15 ch30 ch14 ch29 ch13 tcbr4(25) *=ch1 and ch17 should be set to one to allow the internal ts1 register to create the cas multiframe alignment word and spare/remote alarm bits. 9.2 hardware based signaling receive side hardware signaling is supported through a mode called signaling re-insertion which is invoked by setting the rsre control bit high (ccr3.3=1). in this mode, the user will provide a multiframe sync at the rsync pin and the signaling data will be re-aligned at the rser output according to this applied multiframe boundary. in this mode, the elastic store must be enabled and the backplane clock must be 2.048 mhz. the signaling data in the two multiframe buffer will be frozen in a known good state upon either a loss of synchronization (oof event), carrier loss, or frame slip. to allow this freeze action to occur, the rfe control bit (ccr2.0) should be set high. the user can force a freeze by setting the rff control bit (ccr2.1) high. setting the rff bit high causes the same freezing action as if a loss of synchronization, carrier loss, or slip has occurred. the 2 multiframe buffer provides an approximate 1 multiframe delay in the signaling bits provided at the rser pin (if rsre=1 via ccr3.3). when freezing is enabled (rfe=1), the signaling data will be held in the last known good state until the corrupting error condition subsides. when the error condition sub- sides, the signaling data will be held in the old state for an additional 3 ms to 5 ms before being allowed to be updated with new signaling data. 10. per?channel code generation and loopback each framer in the DS21FT40 can replace data on a channel?by?channel basis in both the transmit and receive directions. the transmit direction is from the backplane to the e1 line and is covered in section 10.1. the receive direction is from the e1 line to the backplane and is covered in section 10.2. 10.1 transmit side code generation in the transmit direction there are two methods by which channel data from the backplane can be overwritten with data generated by the framer. the first method which is covered in section 10.1.1 was a feature contained in the original ds21q43 while the second method which is covered in section 10.1.2 is a new feature of the ds21q44. 10.1.1 simple idle code insertion and per?channel loopback the first method involves using the transmit idle registers (tir1/2/3/4) to determine which of the 32 e1 channels should be overwritten with the code placed in the transmit idle definition register (tidr).
DS21FT40 48 of 87 this method allows the same 8?bit code to be placed into any of the 32 e1 channels. if this method is used, then the ccr3.5 control bit must be set to zero. each of the bit position in the transmit idle registers (tir1/tir2/tir3/tir4) represent a ds0 channel in the outgoing frame. when these bits are set to a one, the corresponding channel will transmit the idle code contained in the transmit idle definition register (tidr). the transmit idle registers (tirs) have an alternate function that allows them to define a per?channel loopback (pclb). if the tirfs control bit (ccr3.5) is set to one, then the tirs will determine which channels (if any) from the backplane should be replaced with the data from the receive side or in other words, off of the e1 line. if this mode is enabled, then transmit and receive clocks and frame syncs must be synchronized. tir1/tir2/tir3: transmit idle registers (address=26 to 29 hex) [also used for per?channel loopback] (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 tir1 (26) ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 tir2 (27) ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 tir3 (28) ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 tir4 (29) symbols positions name and description ch1 - 32 tir1.0 - 4.7 transmit idle code insertion control bits. 0 = do not insert the idle code in the tidr into this channel 1 = insert the idle code in the tidr into this channel note: if ccr3.5=1, then a zero in the tirs implies that channel data is to be sourced from tser and a one implies that channel data is to be sourced from the output of the receive side framer (i.e., per?channel loopback; see figure 1?2). tidr: transmit idle definition register (address=2a hex) (msb) (lsb) tidr7 tidr6 tidr5 tidr4 tidr3 tidr2 tidr1 tidr0 symbols position name and description tidr7 tidr.7 msb of the idle code (this bit is transmitted first) tidr0 tidr.0 lsb of the idle code (this bit is transmitted last) 10.1.2 per?channel code insertion the second method involves using the transmit channel control registers (tcc1/2/3/4) to determine which of the 32 e1 channels should be overwritten with the code placed in the transmit channel registers (tc1 to tc32). this method is more flexible than the first in that it allows a different 8?bit code to be placed into each of the 32 e1 channels.
DS21FT40 49 of 87 tc1 to tc32: transmit channel registers (address=60 to 7f hex) (for brevity, only channel one is shown; see table 3-1 for other register address) (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 tc1 (60) symbols position name and description c7 tc1.7 msb of the code (this bit is transmitted first) c0 tc1.0 lsb of the code (this bit is transmitted last) tcc1/tcc2/tcc3/tcc4: transmit channel control register (address=a0 to a3 hex) (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 tcc1 (a0) ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 tcc2 (a1) ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 tcc3 (a2) ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 tcc4 (a3) symbols position name and description ch1 - 32 tcc1.0 - 4.7 transmit code insertion control bits 0 = do not insert data from the tc register into the transmit data stream 1 = insert data from the tc register into the transmit data stream 10.2 receive side code generation on the receive side, the receive channel control registers (rcc1/2/3/4) are used to determine which of the 32 e1 channels off of the e1 line and going to the backplane should be overwritten with the code placed in the receive channel registers (rc1 to rc32). this method allows a different 8?bit code to be placed into each of the 32 e1 channels. rc1 to rc32: receive channel registers (address=80 to 9f hex) (for brevity, only channel one is shown; see table 3-1 for other register address) (msb) (lsb) c7 c6 c5 c4 c3 c2 c1 c0 rc1 (80) symbols position name and description c7 rc1.7 msb of the code (this bit is sent first to the backplane) c0 rc1.0 lsb of the code (this bit is sent last to the backplane)
DS21FT40 50 of 87 rcc1/rcc2/rcc3/rcc4: receive channel control register (address = a4 to a7 hex) (msb) (lsb) ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 rcc1 (a4) ch16 ch15 ch14 ch13 ch12 ch11 ch10 ch9 rcc2 (a5) ch24 ch23 ch22 ch21 ch20 ch19 ch18 ch17 rcc3 (a6) ch32 ch31 ch30 ch29 ch28 ch27 ch26 ch25 rcc4 (a7) symbols position name and description ch1 - 32 rcc1.0 - 4.7 receive code insertion control bits 0 = do not insert data from the rc register into the receive data stream 1 = insert data from the rc register into the receive data stream 11. clock blocking registers the receive channel blocking registers (rcbr1 / rcbr2 / rcbr3 / rcbr4) and the transmit channel blocking registers (tcbr1 / tcbr2 / tcbr3 / tcbr4) control rchblk and tchblk pins on the ds21q44 die, respectively. the rchblk and tchblk pins are not bonded out on the DS21FT40 module. however, the transmit channel blocking registers have an alternate function that is supported by the module. via the ccr3.6 bit, the user has the option to use the tcbrs to determine on a channel by channel basis, which signaling bits are to be inserted via the tsrs and which are to be sourced from the tser. if ccr3.6=1, then a zero in the tcbrs implies that signaling data is to be sourced from and a one implies that signaling data for that channel is to be sourced from the transmit signaling (ts) registers. see definition below. see the timing in section 16 for an example. the receive channel blocking registers provide no function for the DS21FT40 and should be cleared to zero. tcbr1/tcbr2/tcbr3/tcbr4: definition when ccr3.6=1 (msb) (lsb) ch20 ch4 ch19 ch3 ch18 ch2 ch17* ch1* tcbr1 (22) ch24 ch8 ch23 ch7 ch22 ch6 ch21 ch5 tcbr2 (23) ch28 ch12 ch27 ch11 ch26 ch10 ch25 ch9 tcbr3 (24) ch32 ch16 ch31 ch15 ch30 ch14 ch29 ch13 tcbr4 (25) *=ch1 and ch17 should be set to one to allow the internal ts1 register to create the cas multiframe alignment word and spare/remote alarm bits. 12. elastic stores operation each framer in the DS21FT40 contains dual two?frame (512 bits) elastic stores, one for the receive direction, and one for the transmit direction. these elastic stores have two main purposes. first, they can be used to rate convert the e1 data stream to 1.544 mbps (or a multiple of 1.544 mbps) which is the t1 rate. secondly, they can be used to absorb the differences in frequency and phase between the e1 data stream and an asynchronous (i.e., not frequency locked) backplane clock which can be 1.544 mhz or 2.048 mhz. the backplane clock can burst at rates up to 8.192 mhz. both elastic stores contain full controlled slip capability which is necessary for this second purpose. both elastic stores within a framer are fully independent and no restrictions apply to the sourcing of the various clocks that are applied to them. the transmit side elastic store can be enabled whether the receive elastic store is enabled or
DS21FT40 51 of 87 disabled and vice versa. also, each elastic store can interface to either a 1.544 mhz or 2.048 mhz backplane without regard to the backplane rate the other elastic store is interfacing. two mechanisms are available to the user for resetting the elastic stores. the elastic store reset (ccr6.0 & ccr6.1) function forces the elastic stores to a depth of one frame unconditionally. data is lost during the reset. the second method, the elastic store align ( ccr5.5 & ccr5.6) forces the elastic store depth to a minimum depth of half a frame only if the current pointer separation is already less then half a frame. if a realignment occurs data is lost. in both mechanisms, independent resets are provided for both the receive and transmit elastic stores. 12.1 receive side if the receive side elastic store is enabled (rcr2.1=1), then the user must provide either a 1.544 mhz (rcr2.2 =0) or 2.048 mhz (rcr2.2=1) clock at the rsysclk pin. the user has the option of either providing a frame/multiframe sync at the rsync pin (rcr1.5=1) or having the rsync pin provide a pulse on frame/multiframe boundaries (rcr1.5=0). if the user wishes to obtain pulses at the frame boundary, then rcr1.6 must be set to zero and if the user wishes to have pulses occur at the multiframe boundary, then rcr1.6 must be set to one. if the elastic store is enabled, then either cas (rcr1.7=0) or crc4 (rcr1.7=1) multiframe boundaries will be indicated via the rmsync output. if the user selects to apply a 1.544 mhz clock to the rsysclk pin, then every fourth channel of the received e1 data will be deleted and a f?bit position (which will be forced to one) will be inserted. hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be deleted from the received e1 data stream). see section 16 for timing details. if the 512?bit elastic buffer either fills or empties, a controlled slip will occur. if the buffer empties, then a full frame of data (256?bits) will be repeated at rser and the sr1.4 and rir.3 bits will be set to a one. if the buffer fills, then a full frame of data will be deleted and the sr1.4 and rir.4 bits will be set to a one. 12.2 transmit side the operation of the transmit elastic store is very similar to the receive side. the transmit side elastic store is enabled via ccr3.7. a 1.544 mhz (ccr3.1=0) or 2.048 mhz (ccr3.1=1) clock can be applied to the tsysclk input. the tsysclk can be a bursty clock with rates up to 8.192 mhz. if the user selects to apply a 1.544 mhz clock to the tsysclk pin, then the data sampled at tser will be ignored every fourth channel. hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24, and 28) will be ignored. the user must supply a 8 khz frame sync pulse to the tssync input. see section 16 for timing details. controlled slips in the transmit elastic store are reported in the sr2.0 bit and the direction of the slip is reported in the rir.6 and rir.7 bits. 13. additional (sa) and international (si) bit operation each framer in the DS21FT40 provides for access to both the sa and the si bits via two different methods. the first method involves using the internal raf/rnaf and taf/tnaf registers and is discussed in section 13.1. the second method, which is covered in section 13.2, involves an expanded version of the first method. 13.1 internal register scheme based on double?frame on the receive side, the raf and rnaf registers will always report the data as it received in the additional and international bit locations. the raf and rnaf registers are updated with the setting of the receive align frame bit in status register 2 (sr2.6). the host can use the sr2.6 bit to know when to read the raf and rnaf registers. it has 250 us to retrieve the data before it is lost.
DS21FT40 52 of 87 on the transmit side, data is sampled from the taf and tnaf registers with the setting of the transmit align frame bit in status register 2 (sr2.3). the host can use the sr2.3 bit to know when to update the taf and tnaf registers. it has 250 us to update the data or else the old data will be retransmitted. data in the si bit position will be overwritten if the framer is programmed: (1) to source the si bits from the tser pin, (2) in the crc4 mode, or (3) have automatic e?bit insertion enabled. data in the sa bit position will be overwritten if any of the tcr2.3 to tcr2.7 bits are set to one. please see the register descriptions for tcr1 and tcr2 and the transmit data flow diagram in section 16 for more details. raf: receive align frame register (address=2f hex) (msb) (lsb) si0011011 symbols position name and description si raf.7 international bit. 0 raf.6 frame alignment signal bit. 0 raf.5 frame alignment signal bit. 1 raf.4 frame alignment signal bit. 1 raf.3 frame alignment signal bit. 0 raf.2 frame alignment signal bit. 1 raf.1 frame alignment signal bit 1 raf.0 frame alignment signal bit. rnaf: receive non?align frame register (address=1f hex) (msb) (lsb) si 1 a sa4 sa5 sa6 sa7 sa8 symbols position name and description si rnaf.7 international bit. 1 rnaf.6 frame non?alignment signal bit. a rnaf.5 remote alarm. sa4 rnaf.4 additional bit 4. sa5 rnaf.3 additional bit 5. sa6 rnaf.2 additional bit 6. sa7 rnaf.1 additional bit 7. sa8 rnaf.0 additional bit 8.
DS21FT40 53 of 87 taf: transmit align frame register (address=20 hex) (msb) (lsb) si0011011 [must be programmed with the 7 bit fas word; the DS21FT40 does not automatically set these bits] symbols position name and description si taf.7 international bit. 0 taf.6 frame alignment signal bit. 0 taf.5 frame alignment signal bit. 1 taf.4 frame alignment signal bit. 1 taf.3 frame alignment signal bit. 0 taf.2 frame alignment signal bit. 1 taf.1 frame alignment signal bit. 1 taf.0 frame alignment signal bit. tnaf: transmit non?align frame register (address=21 hex) (msb) (lsb) si 1 a sa4 sa5 sa6 sa7 sa8 [bit 2 must be programmed to one; the DS21FT40 does not automatically set this bit] symbols position name and description si tnaf.7 international bit. 1 tnaf.6 frame non?alignment signal bit. a tnaf.5 remote alarm (used to transmit the alarm). sa4 tnaf.4 additional bit 4. sa5 tnaf.3 additional bit 5. sa6 tnaf.2 additional bit 6. sa7 tnaf.1 additional bit 7. sa8 tnaf.0 additional bit 8. 13.2 internal register scheme based on crc4 multiframe on the receive side, there is a set of eight registers (rsiaf, rsinaf, rra, rsa4 to rsa8) that report the si and sa bits as they are received. these registers are updated with the setting of the receive crc4 multiframe bit in status register 2 (sr2.1). the host can use the sr2.1 bit to know when to read these registers. the user has 2 ms to retrieve the data before it is lost. the msb of each register is the first received. please see the register descriptions below and the transmit data flow diagram in section 16 for more details. on the transmit side, there is also a set of eight registers (tsiaf, tsinaf, tra, tsa4 to tsa8) that via the transmit sa bit control register (tsacr), can be programmed to insert both si and sa data. data is sampled from these registers with the setting of the transmit multiframe bit in status register 2 (sr2.5). the host can use the sr2.5 bit to know when to update these registers. it has 2 ms to update the data or else the old data will be retransmitted. the msb of each register is the first bit transmitted. please see the register descriptions below and the transmit data flow diagram in section 16 for more details.
DS21FT40 54 of 87 register name address (hex) function rsiaf 58 the eight si bits in the align frame. rsinaf 59 the eight si bits in the non?align frame. rra 5a the eight reportings of the receive remote alarm (ra). rsa4 5b the eight sa4 reported in each crc4 multiframe. rsa5 5c the eight sa5 reported in each crc4 multiframe. rsa6 5d the eight sa6 reported in each crc4 multiframe. rsa7 5e the eight sa7 reported in each crc4 multiframe. rsa8 5f the eight sa8 reported in each crc4 multiframe. tsiaf 50 the eight si bits to be inserted into the align frame. tsinaf 51 the eight si bits to be inserted into the non?align frame. tra 52 the eight settings of remote alarm (ra). tsa4 53 the eight sa4 settings in each crc4 multiframe. tsa5 54 the eight sa5 settings in each crc4 multiframe. tsa6 55 the eight sa6 settings in each crc4 multiframe. tsa7 56 the eight sa7 settings in each crc4 multiframe. tsa8 57 the eight sa8 settings in each crc4 multiframe. tsacr: transmit sa bit control register (address=1c hex) (msb) (lsb) siaf sinaf ra sa4 sa5 sa6 sa7 sa8 symbols position name and description siaf tsacr.7 international bit in align frame insertion control bit. 0=do not insert data from the tsiaf register into the transmit data stream. 1=insert data from the tsiaf register into the transmit data stream. sinaf tsacr.6 international bit in non?align frame insertion control bit. 0=do not insert data from the tsinaf register into the transmit data stream. 1=insert data from the tsinaf register into the transmit data stream. ra tsacr.5 remote alarm insertion control bit. 0=do not insert data from the tra register into the transmit data stream. 1=insert data from the tra register into the transmit data stream. sa4 tsacr.4 additional bit 4 insertion control bit. 0=do not insert data from the tsa4 register into the transmit data stream. 1=insert data from the tsa4 register into the transmit data stream.
DS21FT40 55 of 87 symbols position name and description sa5 tsacr.3 additional bit 5 insertion control bit. 0=do not insert data from the tsa5 register into the transmit data stream. 1=insert data from the tsa5 register into the transmit data stream. sa6 tsacr.2 additional bit 6 insertion control bit. 0=do not insert data from the tsa6 register into the transmit data stream. 1=insert data from the tsa6 register into the transmit data stream. sa7 tsacr.1 additional bit 7 insertion control bit. 0=do not insert data from the tsa7 register into the transmit data stream. 1=insert data from the tsa7 register into the transmit data stream. sa8 tsacr.0 additional bit 8 insertion control bit. 0=do not insert data from the tsa8 register into the transmit data stream. 1=insert data from the tsa8 register into the transmit data stream. 14. hdlc controller for the sa bits or ds0 each framer in the DS21FT40 has the ability to extract/insert data from/ into the sa bit positions (sa4 to sa8) or from/to any multiple of ds0 channels each framer contains a complete hdlc controller and this operation is covered in section 14.1. 14.1 general overview each framer contains a complete hdlc controller with 64?byte buffers in both the transmit and receive directions. the hdlc controller performs all the necessary overhead for generating and receiving a hdlc formatted message. the hdlc controller automatically generates and detects flags, generates and checks the crc check sum, generates and detects abort sequences, stuffs and destuffs zeros (for transparency), and byte aligns to the hdlc data stream. there are eleven registers that the host will use to operate and control the operation of the hdlc controller. a brief description of the registers is shown in table 14-1.
DS21FT40 56 of 87 hdlc controller register list table 14-1 name function hdlc control register (hcr) general control over the hdlc and boc controllers hdlc status register (hsr) key status information for both transmit and receive directions hdlc interrupt mask register (himr) allows/stops status bits to/from causing an interrupt receive hdlc information register (rhir) status information on receive hdlc controller receive hdlc fifo register (rhfr) access to 64?byte hdlc fifo in receive direction receive hdlc ds0 control register 1 (rdc1) receive hdlc ds0 control register 2 (rdc2) controls the hdlc function when used on ds0 channels transmit hdlc information register (thir) status information on transmit hdlc controller transmit boc register (tboc) enables/disables transmission of boc codes transmit hdlc fifo register (thfr) access to 64?byte hdlc fifo in transmit direction transmit hdlc ds0 control register 1 (tdc1) transmit hdlc ds0 control register 2 (tdc2) controls the hdlc function when used on ds0 channels 14.2 hdlc status registers three of the hdlc controller registers (hsr, rhir, and thir) provide status information. when a particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be set to a one. some of the bits in these three status registers are latched and some are real time bits that are not latched. section 14.4 contains register descriptions that list which bits are latched and which are not. with the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads that bit. the bit will be cleared when it is read and it will not be set again until the event has occurred again. the real time bits report the current instantaneous conditions that are occurring and the history of these bits is not latched.
DS21FT40 57 of 87 like the other status registers in the framer, the user will always proceed a read of any of the three registers with a write. the byte written to the register will inform the framer which of the latched bits the user wishes to read and have cleared (the real time bits are not affected by writing to the status register). the user will write a byte to one of these registers, with a one in the bit positions he or she wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on. when a one is written to a bit location, the read register will be updated with current value and it will be cleared. when a zero is written to a bit position, the read register will not be updated and the previous value will be held. a write to the status and information registers will be immediately followed by a read of the same register. the read result should be logically and?ed with the mask byte that was just written and this value should be written back into the same register to insure that bit does indeed clear. this second write step is necessary because the alarms and events in the status registers occur asynchronously in respect to their access via the parallel port. this write?read?write (for polled driven access) or write?read (for interrupt driven access) scheme allows an external microcontroller or microprocessor to individually poll certain bits without disturbing the other bits in the register. this operation is key in controlling the DS21FT40 with higher?order software languages. like the sr1 and sr2 status registers, the hsr register has the unique ability to initiate a hardware interrupt via the int* output pin. each of the events in the hsr can be either masked or unmasked from the interrupt pin via the hdlc interrupt mask register (himr). interrupts will force the int* pin low when the event occurs. the int* pin will be allowed to return high (if no other interrupts are present) when the user reads the event bit that caused the interrupt to occur. 14.3 basic operation details as a basic guideline for interpreting and sending hdlc messages, the following sequences can be applied: receive a hdlc message 1. enable rps interrupts. 2. wait for interrupt to occur. 3. disable rps interrupt and enable either rpe, rne, or rhalf interrupt. 4. read rhir to obtain rempty status. a. if rempty=0, then record obyte, cbyte, and pok bits and then read the fifo a1. if cbyte=0 then skip to step 5 a2. if cbyte=1 then skip to step 7 b. if rempty=1, then skip to step 6 5. repeat step 4. 6. wait for interrupt, skip to step 4. 7. if pok=0, then discard whole packet, if pok=1, accept the packet. 8. disable rpe, rne, or rhalf interrupt, enable rps interrupt and return to step 1.
DS21FT40 58 of 87 transmit a hdlc message 1. make sure hdlc controller is done sending any previous messages and is current sending flags by checking that the fifo is empty by reading the tempty status bit in the thir register. 2. enable either the thalf or tnf interrupt. 3. read thir to obtain tfull status. a. if tfull=0, then write a byte into the fifo and skip to next step (special case occurs when the last byte is to be written, in this case set teom=1 before writing the byte and then skip to step 6) b. if tfull=1, then skip to step 5 4. repeat step 3. 5. wait for interrupt, skip to step 3. 6. disable thalf or tnf interrupt and enable tmend interrupt. 7. wait for an interrupt, then read tudr status bit to make sure packet was transmitted correctly. 14.4 hdlc register description hcr: hdlc control register (address=b0 hex) (msb) (lsb) ? rhr tfs thr tabt teom tzsd tcrcd symbols position name and description ? hcr.7 not assigned. should be set to zero. rhr hcr.6 receive hdlc reset. a 0 to 1 transition will reset the receive hdlc controller. must be cleared and set again for a subsequent reset. tfs hcr.5 transmit flag/idle select. 0 = 7eh. 1 = ffh. thr hcr.4 transmit hdlc reset. a 0 to 1 transition will reset the transmit hdlc controller. must be cleared and set again for a subsequent reset. tabt hcr.3 transmit abort. a 0 to 1 transition will cause the fifo contents to be dumped and one feh abort to be sent followed by 7eh or ffh flags/idle until a new packet is initiated by writing new data into the fifo. must be cleared and set again for a subsequent abort to be sent. teom hcr.2 transmit end of message. should be set to a one just before the last data byte of a hdlc packet is written into the transmit fifo at thfr. the hdlc controller will clear this bit when the last byte has been transmitted. tzsd hcr.1 transmit zero stuffer defeat. overrides internal enable. 0 = enable the zero stuffer (normal operation). 1 = disable the zero stuffer. tcrcd hcr.0 transmit crc defeat. 0 = enable crc generation (normal operation). 1 = disable crc generation.
DS21FT40 59 of 87 hsr: hdlc status register (address=b1 hex) (msb) (lsb) ? rpe rps rhalf rne thalf tnf tmend symbols position name and description ? hsr.7 not assigned. should be set to zero. rpe hsr.6 receive packet end. set when the hdlc controller detects either the finish of a valid message (i.e., crc check complete) or when the controller has experienced a message fault such as a crc checking error, or an overrun condition, or an abort has been seen. the setting of this bit prompts the user to read the rhir register for details. rps hsr.5 receive packet start. set when the hdlc controller detects an opening byte. the setting of this bit prompts the user to read the rhir register for details. rhalf hsr.4 receive fifo half full. set when the receive 64?byte fifo fills beyond the half way point. the setting of this bit prompts the user to read the rhir register for details. rne hsr.3 receive fifo not empty. set when the receive 64?byte fifo has at least one byte available for a read. the setting of this bit prompts the user to read the rhir register for details. thalf hsr.2 transmit fifo half empty. set when the transmit 64?byte fifo empties beyond the half way point. the setting of this bit prompts the user to read the thir register for details. tnf hsr.1 transmit fifo not full. set when the transmit 64?byte fifo has at least one byte available. the setting of this bit prompts the user to read the thir register for details. tmend hsr.0 transmit message end. set when the transmit hdlc controller has finished sending a message. the setting of this bit prompts the user to read the thir register for details. note: the rpe, rps, and tmend bits are latched and will be cleared when read. himr: hdlc interrupt mask register (address=b2 hex) (msb) (lsb) ? rpe rps rhalf rne thalf tnf tmend symbols position name and description ? himr.7 not assigned. should be set to zero. rpe himr.6 receive packet end. 0 = interrupt masked. 1 = interrupt enabled. rps himr.5 receive packet start. 0 = interrupt masked. 1 = interrupt enabled.
DS21FT40 60 of 87 symbols position name and description rhalf himr.4 receive fifo half full. 0 = interrupt masked. 1 = interrupt enabled. rne himr.3 receive fifo not empty. 0 = interrupt masked. 1 = interrupt enabled. thalf himr.2 transmit fifo half empty. 0 = interrupt masked. 1 = interrupt enabled. tnf himr.1 transmit fifo not full. 0 = interrupt masked. 1 = interrupt enabled. tmend himr.0 transmit message end. 0 = interrupt masked. 1 = interrupt enabled. rhir: receive hdlc information register (address=b3 hex) (msb) (lsb) rabt rcrce rovr rvm rempty pok cbyte obyte symbols position name and description rabt rhir.7 abort sequence detected. set whenever the hdlc controller sees 7 or more ones in a row. rcrce rhir.6 crc error. set when the crc checksum is in error. rovr rhir.5 overrun. set when the hdlc controller has attempted to write a byte into an already full receive fifo. rvm rhir.4 valid message. set when the hdlc controller has detected and checked a complete hdlc packet. rempty rhir.3 empty. a real?time bit that is set high when the receive fifo is empty. pok rhir.2 packet ok. set when the byte available for reading in the receive fifo at rhfr is the last byte of a valid message (and hence no abort was seen, no overrun occurred, and the crc was correct). cbyte rhir.1 closing byte. set when the byte available for reading in the receive fifo at rfdl is the last byte of a message (whether the message was valid or not). obyte rhir.0 opening byte. set when the byte available for reading in the receive fifo at rhfr is the first byte of a message. note: the rabt, rcrce, rovr, and rvm bits are latched and will be cleared when read.
DS21FT40 61 of 87 rhfr: receive hdlc fifo register (address=b4 hex) (msb) (lsb) hdlc7 hdlc6 hdlc5 hdlc4 hdlc3 hdlc2 hdlc1 hdlc0 symbols position name and description hdlc7 rhfr.7 hdlc data bit 7. msb of a hdlc packet data byte. hdlc6 rhfr.6 hdlc data bit 6. hdlc5 rhfr.5 hdlc data bit 5. hdlc4 rhfr.4 hdlc data bit 4. hdlc3 rhfr.3 hdlc data bit 3. hdlc2 rhfr.2 hdlc data bit 2. hdlc1 rhfr.1 hdlc data bit 1. hdlc0 rhfr.0 hdlc data bit 0. lsb of a hdlc packet data byte. thir: transmit hdlc information register (address=b6 hex) (msb) (lsb) ?????emptytfulludr symbols position name and description ? thir.7 not assigned. could be any value when read. ? thir.6 not assigned. could be any value when read. ? thir.5 not assigned. could be any value when read. ? thir.4 not assigned. could be any value when read. ? thir.3 not assigned. could be any value when read. tempty thir.2 transmit fifo empty. a real?time bit that is set high when the fifo is empty. tfull thir.1 transmit fifo full. a real?time bit that is set high when the fifo is full. udr thir.0 underrun. set when the transmit fifo unwantedly empties out and an abort is automatically sent. note: the udr bit is latched and will be cleared when read.
DS21FT40 62 of 87 thfr: transmit hdlc fifo register (address=b7 hex) (msb) (lsb) hdlc7 hdlc6 hdlc5 hdlc4 hdlc3 hdlc2 hdlc1 hdlc0 symbols position name and description hdlc7 thfr.7 hdlc data bit 7. msb of a hdlc packet data byte. hdlc6 thfr.6 hdlc data bit 6. hdlc5 thfr.5 hdlc data bit 5. hdlc4 thfr.4 hdlc data bit 4. hdlc3 thfr.3 hdlc data bit 3. hdlc2 thfr.2 hdlc data bit 2. hdlc1 thfr.1 hdlc data bit 1. hdlc0 thfr.0 hdlc data bit 0. lsb of a hdlc packet data byte. rdc1: receive hdlc ds0 control register 1 (address=b8 hex) (msb) (lsb) rhs rsads rds0m rd4 rd3 rd2 rd1 rd0 symbols position name and description rhs rdc1.7 receive hdlc source 0 = sa bits defined by rcr2.3 to rcr2.7. 1 = sa bits or ds0 channels defined by rdc1 (see bits defined below). rsads rdc1.6 receive sa bit / ds0 select. 0 = route sa bits to the hdlc controller. rd0 to rd4 defines which sa bits are to be routed. rd4 corresponds to sa4, rd3 to sa5, rd2 to sa6, rd1 to sa7 and rd0 to sa8. 1 = route ds0 channels into the hdlc controller. rdc1.5 is used to determine how the ds0 channels are selected. rds0m rdc1.5 ds0 selection mode. 0 = utilize the rd0 to rd4 bits to select which single ds0 channel to use. 1 = utilize the rchblk control registers to select which ds0 channels to use. this option is not applicable for the DS21FT40. rd4 rdc1.4 ds0 channel select bit 4. msb of the ds0 channel select. rd3 rdc1.3 ds0 channel select bit 3. rd2 rdc1.2 ds0 channel select bit 2. rd1 rdc1.1 ds0 channel select bit 1. rd0 rdc1.0 ds0 channel select bit 0. lsb of the ds0 channel select.
DS21FT40 63 of 87 rdc2: receive hdlc ds0 control register 2 (address=b9 hex) (msb) (lsb) rdb8 rdb7 rdb6 rdb5 rdb4 rdb3 rdb2 rdb1 symbols position name and description rdb8 rdc2.7 ds0 bit 8 suppress enable. msb of the ds0. set to one to stop this bit from being used. rdb7 rdc2.6 ds0 bit 7 suppress enable. set to one to stop this bit from being used. rdb6 rdc2.5 ds0 bit 6 suppress enable. set to one to stop this bit from being used. rdb5 rdc2.4 ds0 bit 5 suppress enable. set to one to stop this bit from being used. rdb4 rdc2.3 ds0 bit 4 suppress enable. set to one to stop this bit from being used. rdb3 rdc2.2 ds0 bit 3 suppress enable. set to one to stop this bit from being used. rdb2 rdc2.1 ds0 bit 2 suppress enable. set to one to stop this bit from being used. rdb1 rdc2.0 ds0 bit 1 suppress enable. lsb of the ds0. set to one to stop this bit from being used. tdc1: transmit hdlc ds0 control register 1 (address = ba hex) (msb) (lsb) the tsads tds0m td4 td3 td2 td1 td0 symbols position name and description the tdc1.7 transmit hdlc enable. 0 = disable hdlc controller (no data inserted by hdlc controller into the transmit data stream) 1 = enable hdlc controller to allow insertion of hdlc data into either the sa position or multiple ds0 channels as defined by tdc1 (see bit definitions below). tsads tdc1.6 transmit sa bit / ds0 select. this bit is ignored if tdc1.7 is set to zero. 0 = route sa bits from the hdlc controller. td0 to td4 defines which sa bits are to be routed. td4 corresponds to sa4, td3 to sa5, td2 to sa6, td1 to sa7 and td0 to sa8. 1 = route ds0 channels from the hdlc controller. tdc1.5 is used to determine how the ds0 channels are selected. tds0m tdc1.5 ds0 selection mode. not applicable for the DS21FT40. should be cleared to zero.
DS21FT40 64 of 87 symbols position name and description td4 tdc1.4 ds0 channel select bit 4. msb of the ds0 channel select. td3 tdc1.3 ds0 channel select bit 3. td2 tdc1.2 ds0 channel select bit 2. td1 tdc1.1 ds0 channel select bit 1. td0 tdc1.0 ds0 channel select bit 0. lsb of the ds0 channel select. tdc2: transmit hdlc ds0 control register 2 (address = bb hex) (msb) (lsb) tdb8 tdb7 tdb6 tdb5 tdb4 tdb3 tdb2 tdb1 symbols position name and description tdb8 tdc2.7 ds0 bit 8 suppress enable. msb of the ds0. set to one to stop this bit from being used. tdb7 tdc2.6 ds0 bit 7 suppress enable. set to one to stop this bit from being used. tdb6 tdc2.5 ds0 bit 6 suppress enable. set to one to stop this bit from being used. tdb5 tdc2.4 ds0 bit 5 suppress enable. set to one to stop this bit from being used. tdb4 tdc2.3 ds0 bit 4 suppress enable. set to one to stop this bit from being used. tdb3 tdc2.2 ds0 bit 3 suppress enable. set to one to stop this bit from being used. tdb2 tdc2.1 ds0 bit 2 suppress enable. set to one to stop this bit from being used. tdb1 tdc2.0 ds0 bit 1 suppress enable. lsb of the ds0. set to one to stop this bit from being used. 15. interleaved pcm bus operation in many architectures, the outputs of individual framers are combined into higher speed serial buses to simplify transport across the system. the DS21FT40 can be configured to allow each framer?s data and signaling busses to be multiplexed into higher speed data and signaling busses eliminating external hardware saving board space and cost. in particular, the four framers associated with each ds21q44 die can be combined. the interleaved pcm bus option supports two bus speeds and interleave modes. the 4.096 mhz bus speed allows two framers to share a common bus. the 8.192 mhz bus speed allows all four of the framers for each ds21q44 die to share a common bus. framers can interleave their data either on byte or frame boundaries. framers that share a common bus must be configured through software and require several device pins to be connected together externally (see figures 15-1 & 15-2). each framer?s elastic stores must be enabled and configured for 2.048 mhz operation. the signal rsync must be configured as an input on each framer.
DS21FT40 65 of 87 for all bus configurations, one framer will be configured as the master device and the remaining framers on the shared bus will be configured as slave devices. refer to the ibo register description below for more detail. in the 4.096 mhz bus configuration there is one master and one slave per bus. figure 15-1 shows the ds21q44 configured to support two 4.096 mhz buses. bus 1 consists of framers 0 and 1. bus 2 consists of framers 2 and 3. framers 0 and 2 are programmed as master devices. framers 1 and 3 are programmed as slave devices. in the 8.192 mhz bus configuration there is one master and three slaves. figure 15-2 shows the ds21q44 configured to support a 8.192 mhz bus. framer 0 is programmed as the master device. framers 1, 2 and 3 are programmed as slave devices. consult timing diagrams in section 16 for additional information. when using the frame interleave mode, all framers that share an interleaved bus must have receive signals (rpos & rneg) that are synchronous with each other. the received signals must originate from the same clock reference. this restriction does not apply in the byte interleave mode. ibo: interleave bus operation register (address = b5 hex) (msb) (lsb) ? ? ? ? iboen intsel msel0 msel1 symbols position name and description ? ibo.7 not assigned. should be set to 0. ? ibo.6 not assigned. should be set to 0. ? ibo.5 not assigned. should be set to 0. ? ibo.4 not assigned. should be set to 0. iboen ibo.3 interleave bus operation enable 0 = interleave bus operation disabled. 1 = interleave bus operation enabled. intsel ibo.2 interleave type select 0 = byte interleave. 1 = frame interleave. msel0 ibo.1 master device bus select bit 0 see table 15-1. msel1 ibo.0 master device bus select bit 1 see table 15-1. master device bus select table 15-1 msel1 msel0 function 0 0 slave device. 0 1 master device with 1 slave device (4.096 mhz bus rate) 1 0 master device with 3 slave devices (8.192 mhz bus rate) 11reserved
DS21FT40 66 of 87 4.096 mhz interleaved bus external pin connection example figure 15-1 rsysclk0 tsysclk0 rser0 tser0 rsync0 tssync0 framer 0 rsysclk1 tsysclk1 rser1 tser1 rsync1 tssync1 framer 1 sysclk sync input rser tser bus 1 bus 2 rsysclk2 tsysclk2 rser2 tser2 rsync2 tssync2 framer 2 rsysclk3 tsysclk3 rser3 tser3 rsync3 tssync3 framer 3 sysclk sync input rser tser 8.192 mhz interleaved bus external pin connection example figure 15-2 rsysclk0 tsysclk0 rser0 tser0 rsync0 tssync0 framer 0 rsysclk1 tsysclk1 rser1 tser1 rsync1 tssync1 framer 1 rsysclk2 tsysclk2 rser2 tser2 rsync2 tssync2 framer 2 rsysclk3 tsysclk3 rser3 tser3 rsync3 tssync3 framer 3 sysclk sync input rser tser
DS21FT40 67 of 87 16. timing diagrams receive side timing figure 16-1 12 345 6 7 8 9 10111213141516 frame# 1 12 345 6 14 15 16 2 rsync / rfsync rsync notes: 1. rsync in the frame mode (rcr1.6 = 0) 2. rsync in the multiframe mode (rcr1.6 = 1) 3. this diagram assumes the cas mf begins with the fas word receive side boundary timing (with elastic store disabled) figure 16-2 rclk rsync notes: 1. there is a 6 rclk delay from rpos, rneg to rser 2. shown is a non-align frame boundary lsb msb msb channel 2 rser channel 32 si 1 a sa4 channel 1 sa5 sa6 sa7 sa8 lsb msb channel 2 si 1 a sa4 channel 1 sa5 sa6 sa7 sa8 rpos, rneg 1 lsb
DS21FT40 68 of 87 receive side 1.544 mhz boundary timing (with elastic store enabled) figure 16-3 rser lsb msb f msb lsb rsync rsysclk rsync 1 2 3 channel 23/31 channel 24/32 channel 1/2 notes: 1. data from the e1 channels 1, 5, 9, 13, 17, 21, 25, and 29 is dropped (channel 2 from the e1 link is mapped to channel 1 of the t1 link, etc.) and the f-bit position is added (forced to one) 2. rsync is in the output mode (rcr1.5 = 0) 3. rsync is in the input mode (rcr1.5 = 1) receive side 2.048 mhz boundary timing (with elastic store enabled) figure 16-4 rser lsb msb lsb channel 1 rsync rsysclk rsync channel 31 channel 32 1 2 msb notes: 1. rsync is in the output mode (rcr1.5 = 0) 2. rsync is in the input mode (rcr1.5 = 1)
DS21FT40 69 of 87 receive side interleaved bus operation byte mode timing figure 16-5 rser lsb sysclk rsync framer 3, channel 32 msb lsb framer 0, channel 1 msb lsb framer 1, channel 1 notes: 1. 4.096 mhz bus configuration. 2. 8.192 mhz bus configuration. 3. rsync is in the input mode (rcr1.5 = 1). 3 rser rsync rsig fr1 ch32 fr0 ch1 fr1 ch1 fr0 ch2 fr1 ch2 rser fr2 ch32 fr3 ch32 fr0 ch1 fr1 ch1 fr2 ch1 fr3 ch1 fr0 ch2 fr1 ch2 fr2 ch2 fr3 ch2 fr1 ch32 fr0 ch1 fr1 ch1 fr0 ch2 fr1 ch2 1 1 2 bit detail receive side interleaved bus operation frame mode timing figure 16-6 rser lsb sysclk rsync framer 3, channel 32 msb lsb framer 0, channel 1 msb lsb framer 0, channel 2 notes: 1. 4.096 mhz bus configuration. 2. 8.192 mhz bus configuration. 3. rsync is in the input mode (rcr1.5 = 1). 3 rser rsync fr1 ch1-32 fr0 ch1-32 fr1 ch1-32 rser fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 1 2 bit detail
DS21FT40 70 of 87 transmit side timing figure 16-7 12 345 6 7 8 9 10111213141516 frame# 1 tsync tsync 12 345 6 14 15 16 2 notes: 1. tsync in the frame mode (tcr1.1 = 0) 2. tsync in the multiframe mode (tcr1.1 = 1) 3. this diagram assumes both the cas mf and the crc4 begin with the align frame transmit side timing figure 13.5 transmit side boundary timing (with elastic store disabled) figure 16-8 lsb msb channel 2 channel 1 2 3 tclk tsync tsync a sa4 sa5 sa6 sa7 sa8 notes: 1. there is a 5 tclk delay from tser to tpos and tneg 2. tsync is in the input mode (tcr1.0 = 0) 3. tsync is in the output mode (tcr1.0 = 1) 4. shown is a non-align frame boundary tpos, tneg si 1 lsb msb lsb msb a sa4 sa5 sa6 sa7 sa8 tser si 1 channel 1 msb channel 32 1
DS21FT40 71 of 87 transmit side 1.544 mhz boundary timing (with elastic store enabled) figure 16-9 tser lsb msb lsb channel 1 tsysclk tssync channel 23 channel 24 notes: 1. the f-bit position is ignored by the DS21FT40 msb f-bit transmit side 2.048 mhz boundary timing (with elastic store enabled) figure 16-10 tser lsb msb lsb channel 1 tsysclk tssync channel 31 channel 32 msb
DS21FT40 72 of 87 transmit side interleaved bus operation byte mode timing figure 16-11 tser lsb sysclk tssync framer 3, channel 32 msb lsb framer 0, channel 1 msb lsb framer 1, channel 1 notes: 1. 4.096 mhz bus configuration. 2. 8.192 mhz bus configuration. tser tssync tser fr2 ch32 fr3 ch32 fr0 ch1 fr1 ch1 fr2 ch1 fr3 ch1 fr0 ch2 fr1 ch2 fr2 ch2 fr3 ch2 1 2 bit detail fr1 ch32 fr0 ch1 fr1 ch1 fr0 ch2 fr1 ch2 transmit side interleaved bus operation frame mode timing figure 16-12 tser lsb sysclk tssync framer 3, channel 32 msb lsb framer 0, channel 1 msb lsb framer 0, channel 2 notes: 1. 4.096 mhz bus configuration. 2. 8.192 mhz bus configuration. tser tssync fr1 ch1-32 fr0 ch1-32 fr1 ch1-32 tser fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 fr2 ch1-32 fr3 ch1-32 fr0 ch1-32 fr1 ch1-32 1 2 bit detail
DS21FT40 73 of 87 DS21FT40 framer synchronization flowchart figure 16-13 fas resync criteria met check for >=915 out of 1000 crc4 word errors 8ms time out rlos = 1 set fasrc (rir.1) cas resync criteria met; set casrc (rir.0) fas search fassa = 1 fas sync criteria met fassa = 0 cas sync criteria met cassa = 0 if crc4 is on (ccr1.0 = 1) rlos = 1 if cas is on (ccr1.3 = 0) power up increment crc4 sync counter; crc4sa = 0 crc4 resync criteria met (rir.2) cas multiframe search (if enabled via ccr1.3) cassa = 1 crc4 multiframe search (if enabled via ccr1.0) crc4sa = 1 resync if rcr1.0 = 0 check for fas framing error (depends on rcr1.2) check for cas mf word error sync declared rlos = 0 crc4 sync criteria met; crc4sa = 0; reset crc4 sync counter
DS21FT40 74 of 87 DS21FT40 transmit data flow figure 16-14 si bit insertion control (tcr1.3) timeslot 0 pass-through (tcr1.6) e-bit generation (tcr2.1) sa bit insertion control (tcr2.3 thru tcr2.7) idle code / channel insertion control via tir1/2/3/4 transmit unframed all ones (tcr1.4) or auto ais (ccr2.5) code word generation crc4 enable (ccr1.4) taf tnaf.5-7 tlink ts1 to ts16 tidr tpos, tneg 01 0 1 1 0 01 1 0 01 01 1 0 ais generation transmit signaling all ones (tcr1.2) = register = device pin = selector key: tcbr1/2/3/4 rser (note #1) ccr3.6 tcr1.5 signaling bit insertion control tir function select (ccr3.5) ais generation 01 notes: 1. tclk should be tied to rclk and tsync should be tied to rfsync for data to be properly sourced from rser. 2. auto remote alarm if enabled will only overwrite bit 3 of timeslot 0 in the not align frames if the alarm needs to be sent. sa bit insertion control register (tsacr) 1 0 tsa4 to tsa8 tra tsinaf tsiaf crc4 multiframe alignment word generation (ccr.4) receive side crc4 error detector 01 auto remote alarm generation (ccr2.4) per-channel code generation (tcc1/2/3/4) 01 tc1 to tc32 hdlc engine ds0 data source mux (tdc1/2) 01 tser & tdata taf/tnaf bit mux 01 tnaf.0-4 sa data source mux (tdc1) 01 ds0 monitor tsig hardware signaling insertion (ccr3.2) 01
DS21FT40 75 of 87 17. operating parameters absolute maximum ratings* voltage on any non-supply pin relative to ground ?1.0v to +5.5v supply voltage ?.3v to +3.63v operating temperature for DS21FT40 0oc to 70oc operating temperature for DS21FT40n ?40oc to +85oc storage temperature ?55oc to +125oc soldering temperature see j-std-020a * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0oc to 70oc for DS21FT40; 0oc to +85oc for DS21FT40n) parameter symbol min typ max units notes logic 1 v ih 2.0 5.5 v logic 0 v il ?0.3 +0.8 v supply v dd 2.97 3.63 v capacitance (t a =25oc) parameter symbol min typ max units notes input capacitance c in 5pf output capacitance c out 7pf dc characteristics (0oc to 70oc; v dd = 2.97 to 3.63v for DS21FT40; -40oc to +85oc; v dd = 2.97 to 3.63v for ds21q44n ) parameter symbol min typ max units notes supply current @ 3.3v i dd 75 ma 1 input leakage i il ?1.0 +1.0 a 2 output leakage i lo 1.0 a 3 output current (2.4v) i oh ?1.0 ma output current (0.4v) i ol +4.0 ma notes: 1. tclk=rclk=tsysclk=rsysclk=2.048 mhz; outputs open circuited. 2. 0.0v < v in < v dd . 3. applied to int* when 3?stated.
DS21FT40 76 of 87 ac characteristics ? multiplexed parallel port (mux=1) (0oc to 70oc; v dd = 2.97 to 3.63v for DS21FT40 ?40oc to +85oc; v dd = 2.97 to 3.63v for DS21FT40n) parameter symbol min typ max units notes cycle time t cyc 200 ns pulse width, ds low or rd* high pw el 100 ns pulse width, ds high or rd* low pw eh 100 ns input rise/fall times t r , t f 20 ns r/w* hold time t rwh 10 ns r/w* set up time before ds high t rws 50 ns cs1*, cs2*, cs3*, fso or fs1 set up time before ds, wr* or rd* active t cs 20 ns cs1*, cs2*, cs3*, fso or fs1 hold time t ch 0ns read data hold time t dhr 10 50 ns write data hold time t dhw 0ns muxed address valid to as or ale fall t asl 15 ns muxed address hold time t ahl 10 ns delay time ds, wr* or rd* to as or ale rise t asd 20 ns pulse width as or ale high pw ash 30 ns delay time, as or ale to ds, wr* or rd* t ased 10 ns output data delay time from ds or rd* t ddr 20 80 ns data set up time t dsw 50 ns (see figures 17-1 to 17-3 for details)
DS21FT40 77 of 87 ac characteristics ? non?multiplexed parallel port (mux=0 ) (0oc to 70oc; v dd = 2.97 to 3.63v for DS21FT40; ?40oc to +85oc; v dd = 2.97 to 3.63v for DS21FT40n) parameter symbol min typ max units notes set up time for a0 to a7, fs0 or fs1 valid to cs1*, cs2*, cs3* active t 1 0ns set up time for cs1*, cs2*, cs3* active to either rd*, wr*, or ds* active t 2 0ns delay time from either rd* or ds* active to data valid t 3 75 ns hold time from either rd*, wr*, or ds* inactive to cs1*, cs2*, cs3* inactive t 4 0ns hold time from cs1*, cs2*, cs3* inactive to data bus 3?state t 5 520ns wait time from either wr* or ds* active to latch data t 6 75 ns data set up time to either wr* or ds* inactive t 7 10 ns data hold time from either wr* or ds* inactive t 8 10 ns address hold from either wr* or ds* inactive t 9 10 ns see figures 17?4 to 17-7 for details.
DS21FT40 78 of 87 ac characteristics ? receive side (0oc to 70oc; v dd = 2.97 to 3.63v for DS21FT40; ?40oc to +85oc; v dd = 2.97 to 3.63v for DS21FT40n) parameter symbol min typ max units notes rclk period t cp 488 ns rclk pulse width t ch t cl 75 75 ns ns rsysclk period t sp t sp 122 122 648 488 ns ns 1 2 rsysclk pulse width t sh t sl 50 50 ns ns rsync set up to rsysclk falling t su 20 t sh ?5 ns rsync pulse width t pw 50 ns rpos/rneg set up to rclk falling t su 20 ns rpos/rneg hold from rclk falling t hd 20 ns rsysclk/rclki rise and fall times t r , t f 25 ns delay rclk to rser valid t d1 50 ns delay rclk to rsync t d2 50 ns delay rsysclk to rser valid t d3 50 ns delay rsysclk to rmsync, rsync t d4 50 ns see figures 17-8 to 17-10 for details. notes: 1. rsysclk = 1.544 mhz. 2. rsysclk = 2.048 mhz.
DS21FT40 79 of 87 ac characteristics ? transmit side (0oc to 70oc; v dd = 2.97 to 3.63v for DS21FT40; ?40oc to +85oc; ; v dd = 2.97 to 3.63v for DS21FT40n) parameter symbol min typ max units notes tclk period t cp 488 ns tclk pulse width t ch t cl 75 75 ns ns tclki pulse width t lh t ll 75 75 ns ns tsysclk period t sp t sp 122 122 648 448 ns ns 1 2 tsysclk pulse width t sh t sl 50 50 ns ns tsync or tssync set up to tclk or tsysclk falling t su 20 t ch ?5 or t sh ?5 ns tsync or tssync pulse width t pw 50 ns tser set up to tclk, tsysclk falling t su 20 ns tser hold from tclk, tsysclk falling t hd 20 ns tclk or tsysclk rise and fall times t r , t f 25 ns delay tclk to tpos, tneg valid t dd 50 ns delay tclk to tsync t d2 50 ns see figures 17?11 to 17?13 for details. notes: 1. tsysclk = 1.544 mhz. 2. tsysclk = 2.048 mhz.
DS21FT40 80 of 87 intel bus read ac timing (bts=0 / mux = 1) figure 17-1 ash pw t cyc t asd t asd pw pw eh el t t t t t t ahl ch cs asl ased cs* ad0-ad7 dhr t ddr ale rd* wr* intel bus write timing (bts=0 / mux=1) figure 17-2 ash pw t cyc t asd t asd pw pw eh el t t t t t t t ahl dsw dhw ch cs asl ased cs* ad0-ad7 rd* wr* ale
DS21FT40 81 of 87 motorola bus ac timing (bts = 1 / mux = 1) figure 17-3 t asd ash pw t t asl ahl t cs t asl t t t dsw dhw t ch t t t ddr dhr rwh t ased pw eh t rws ahl pw el t cyc as ds ad0-ad7 (write) ad0-ad7 (read) r/w* cs* intel bus read ac timing (bts=0 / mux=0) figure 17-4 address valid data valid a0 to a7 d0 to d7 wr* cs* rd* 0ns min. 0ns min. 75ns max. 0ns min. 5ns min. / 20ns max. t1 t2 t3 t4 t5
DS21FT40 82 of 87 intel bus write ac timing (bts=0 / mux=0) figure 17-5 address valid a0 to a7 d0 to d7 rd* cs* wr* 0ns min. 0ns min. 75ns min. 0ns min. 10ns min. 10ns min. t1 t2 t6 t4 t7 t8 motorola bus read ac timing (bts=1 / mux=0) figure 17-6 address valid data valid a0 to a7 d0 to d7 r/w* cs* ds 0ns min. 0ns min. 0ns min. 5ns min. / 20ns max. motorola bus read ac timing (bts = 1 / mux = 0) figure 16.12 t1 t2 t3 t4 t5 75ns max.
DS21FT40 83 of 87 motorola bus write ac timing (bts=1 / mux=0) figure 17-7 address valid a0 to a7 d0 to d7 r/w* cs* ds* 0ns min. 0ns min. 75ns min. 0ns min. 10ns min. 10ns min. t1 t2 t6 t4 t7 t8 receive side ac timing figure 17-8 t d1 1 t d2 rser rsync notes: 1. rsync is in the output mode (rcr1.5 = 0). rclk t d2 rmsync msb of channel 1
DS21FT40 84 of 87 receive system side ac timing figure 17-9 t f t r t d3 1 t d4 t t su hd 2 rser / rsig rsync rsync notes: 1. rsync is in the output mode (rcr1.5 = 0) 2. rsync is in the input mode (rcr1.5 = 1) rsysclk sl t t sp sh t t d4 rmsync msb of channel 1 receive line interface ac timing figure 17-10 t f t r rpos, rneg rclk cl t t cp ch t t su t hd
DS21FT40 85 of 87 transmit side ac timing figure 17-11 t f t r 1 tclk tser t t cl t ch cp tsync tsync t d2 t t su hd t hd 2 notes: 1. tsync is in the output mode (tcr1.0 = 1). 2. tsync is in the input mode (tcr1.0 = 0). 3. tser is sampled on the falling edge of tclk when the transmit side elastic store is disabled. t su transmit system side ac timing figure 17-12 t f t r tsysclk tser t t sl t sh sp tssync t t t su hd su notes: 1. tser is only sampled on the falling edge of tsysclk when the transmit side elastic store is enabled. transmit line interface side ac timing figure 17-13 t f t r tclk tpos, tneg t t cl t ch cp t dd
DS21FT40 86 of 87 18. DS21FT40 mechanical dimensions
DS21FT40 87 of 87 power supply de-coupling in a typical pcb layout for the mcm, all of the vdd pins will connect to a common power plane and all the vss lines will connect to a common ground plane. the recommended method for de-coupling is shown below in both schematic and pictorial form. as shown in the pictorial, the capacitors should be symmetrically located about the device. figure 18-1 uses standard capacitors, two .47 uf ceramics and two .01uf ceramics. since vdd and vss signals will typically pass vertically to the power and ground planes of a pcb, the de-coupling caps must be placed as close to the DS21FT40 as possible and routed vertically to power and ground planes. de-coupling scheme using standard tantalum caps. figure 18-1

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